3D Memory Word-Line Precharge Sequencing for Program Interference
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Solution Overview
Problem
The increasing number of memory cell layers in 3D memory structures leads to significant programming interference between word lines due to reduced distances, affecting the programming efficiency of the erased state L0.
Innovation Solution
A method involving a peripheral circuit that sequentially applies precharge voltages to word lines, reducing them to a turn-off voltage in a specific order to create a potential difference in the channel, driving electrons away and maintaining boosting potential, thereby reducing programming interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory string layers is increased to meet growing memory capacity demand, then memory capacity is improved, but programming interference between word lines increases due to reduced distances
Solution Approach 1:
The patent applies preliminary action by sequentially turning off word lines before programming operations. The peripheral circuit turns off word lines in a predetermined sequence before applying program voltage, which prepares the channel by removing electrons in advance and reduces programming interference between adjacent word lines in high-layer 3D memory structures
Solution Approach 2:
The patent changes the voltage parameter dynamically during operations. The peripheral circuit applies different voltage levels (precharge voltage, turn-off voltage, program voltage, verification voltage) at different stages. This parameter change enables the system to maintain low interference during programming by using specific voltage sequences that control electron distribution in the channel
2Productivity
If precharge voltages are applied to all word lines simultaneously, then programming speed is improved, but programming interference between adjacent word lines increases
Solution Approach 1:
The patent segments the word line voltage control into different stages and sequences. Instead of applying precharge voltages to all word lines simultaneously, the peripheral circuit turns off word lines sequentially in a predetermined sequence before programming. This segmentation in time and sequence reduces the overlapping interference between adjacent word lines while maintaining efficient programming operations
Solution Approach 2:
The patent implements periodic action through the sequential turning off of word lines in repeated cycles. The peripheral circuit repeatedly applies the sequence of turning off word lines before each programming operation, creating a periodic pattern that consistently reduces interference. This periodic sequential turn-off ensures that electrons are removed in stages rather than all at once, minimizing interference during the programming process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes programming interference by maintaining channel potential, enhancing the programming efficiency of the erased state L0 and reducing interference during the programming process.
Implementation Method 1
the precharge voltages applied to the plurality of word lines are sequentially reduced to a first turn-off voltage according to the arrangement order of the memory cells coupled to the plurality of word lines in the memory array... generating a potential difference from the first word line to the second word line in the channel
Implementation Method 2
driving the electrons in the channel to move from the direction of the first word line to the direction of the second word line
Data Source
AI summary
The present application discloses a memory, a memory operation method and a memory system. The memory includes: a memory array and a peripheral circuit, wherein the memory array includes a plurality of memory cells coupled to a first bit line and to a plurality of word lines respectively, wherein the plurality of word lines include a selected word line coupled to a memory cell to be programmed; the peripheral circuit is configured to: apply precharge voltages to the plurality of word lines; sequentially reduce the precharge voltages applied to the plurality of word lines to a first turn-off voltage according to the arrangement order of the memory cells coupled to the plurality of word lines in the memory array; apply a program voltage to a selected word line in the plurality of word lines, and apply a turn-on voltage to other word lines in the plurality of word lines.