Memory Array Pre-Charge Calibration for Near-Far Read Energy
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Solution Overview
Problem
Voltage-type read-out schemes for non-volatile memory devices apply uniform pre-charge voltages across different word-line addresses, ignoring the near-far effect of bit-lines, leading to excessive energy consumption in read operations for neural network models.
Innovation Solution
A memory device with a calibration circuit that generates pre-charge signals based on the address of the weights to be read, adjusting the bit line pre-charge time and voltage according to the position of the memory cells, reducing energy consumption by dynamically modulating the bit-line pre-charge time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If uniform pre-charge voltage is applied to all bit-lines, then the read operation is simple to implement, but energy consumption increases significantly due to the near-far effect
Solution Approach 1:
The patent applies different pre-charge voltages to different bit-lines based on their distance from the input/output circuit. Bit-lines closer to the I/O circuit receive lower pre-charge voltages, while those farther away receive higher pre-charge voltages to compensate for the near-far effect, thereby reducing overall energy consumption while maintaining read accuracy
Solution Approach 2:
The patent dynamically adjusts the pre-charge voltage level based on the word-line address being accessed. The pre-charge circuit selects different voltage levels corresponding to different bit-line groups, making the pre-charge operation adaptive rather than static, which optimizes energy consumption for each read operation
2Use of energy by moving object
If different pre-charge voltages are applied to different bit-lines, then energy consumption is reduced, but device complexity increases due to additional control circuits
Solution Approach 1:
The calibration circuit serves multiple functions: it calibrates the pre-charge voltages during initialization and also provides control signals during normal read operations. This multi-functionality reduces the need for separate control circuits, thereby limiting the increase in device complexity while achieving energy reduction
Solution Approach 2:
The patent performs pre-charge voltage calibration during an initialization phase before normal read operations. This preliminary action establishes the appropriate voltage levels and control signal mappings, simplifying subsequent read operations and reducing the complexity of real-time control logic
3Measurement precision
If bit-line pre-charge time is extended, then read accuracy improves, but read throughput decreases due to longer operation time
Solution Approach 1:
The patent changes the pre-charge voltage parameter instead of extending pre-charge time. By applying higher pre-charge voltages to distant bit-lines, the system achieves sufficient signal levels for accurate reading without requiring prolonged pre-charge durations, thereby maintaining both accuracy and throughput
Data Source
AI summary
A memory device includes a memory array storing weights; a pre-charging circuit coupled to the memory array through data lines and charging, in response to a pre-charge signal, at least one data line in the data lines to a read voltage in a read operation to one in the weights; and a calibration circuit generating the pre-charge signal according to an address of the one in the weights.