Memory Device Precharge Controller for Program Speed

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Solution Overview

Problem

The existing memory devices face challenges in reducing the time required for program operations, as the precharge, program, and verify phases are time-consuming and can lead to disturbances in unintended data.

Innovation Solution

The proposed memory device incorporates a precharge controller that monitors the program operation and adjusts the precharge mode for unselected strings based on the target voltage of selected memory cells. Additionally, a select line voltage generator applies either a positive or negative voltage to the second select line, depending on the target voltage, to optimize the precharge phase.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a precharge phase is performed before the program phase to precharge unselected strings, then programming of unselected strings is inhibited, but the time required for the program operation increases

Engineering Contradiction:
Improveprogramming inhibition of unselected stringsVSAvoidprogram operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies dynamics by making the precharge voltage application conditional rather than static. The controller dynamically determines whether to apply precharge voltage to unselected strings based on the target program state. For lower program states, precharge voltage is applied to inhibit programming; for higher program states, precharge voltage is omitted to reduce operation time. This dynamic adaptation resolves the contradiction between reliable programming inhibition and reduced operation time.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of precharge voltage application based on the target program state. By adjusting whether precharge voltage is applied (a binary parameter change) according to the target state, the system optimizes the balance between programming inhibition reliability and operation speed. This parameter change allows the system to adapt its behavior to different programming scenarios.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the precharge phase time is reduced to decrease program operation time, then productivity improves, but disturbances may occur in unselected strings

Engineering Contradiction:
Improveprogram operation speedVSAvoiddisturbances in unselected strings
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent applies parameter changes by adjusting the precharge voltage application strategy based on the target program state. For higher program states where less precharge time is needed, the system changes the parameter to omit precharge voltage entirely, thus reducing operation time while avoiding disturbances that would occur with extended precharging. This selective parameter adjustment resolves the contradiction between speed and disturbance prevention.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies partial action by selectively applying precharge voltage only when necessary (for lower program states) and omitting it when not needed (for higher program states). This partial application of the precharge function achieves the necessary programming inhibition while minimizing operation time and avoiding unnecessary disturbances, thus resolving the contradiction between productivity and harmful effects.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS12333153B2Memory device and operating method of the memory device
Publication Date: 2025.06.17 SK HYNIX INC
  • US12333153B2 patent drawing
  • US12333153B2 patent drawing
  • US12333153B2 patent drawing

AI summary

There are provided a memory device and an operating method of the memory device. The memory device includes: a memory block including first select transistors, memory cells, and second select transistors, which are connected between bit lines and a source line; a precharge controller for monitoring a program operation of the memory cells, and changing a precharge mode of unselected strings among strings included in the memory block according to a monitoring result; and a select line voltage generator for generating a positive voltage or a negative voltage, which is applied to a second select line connected to the second select transistors, according to the precharge mode selected in the precharge controller.