3D Memory Precharge Speed via Source Select Line Floating
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Solution Overview
Problem
As memory devices approach their physical scaling limits, there is a need to improve program speed in semiconductor memory devices, particularly in three-dimensional structures where vertical stacking of memory cells leads to challenges in precharging and programming operations.
Innovation Solution
The semiconductor memory device includes a memory cell array with multiple memory blocks, a peripheral circuit, and control logic that manages the program operation by floating certain select lines during the precharge phase, applying ground voltages strategically, and using select line control switches to isolate unselected memory blocks, thereby minimizing the influence of parasitic capacitance and enhancing precharge speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a program operation is performed on a selected memory block in a 3D memory device, then the program speed can be improved, but parasitic capacitance from unselected memory blocks causes precharge delays and reduces overall efficiency
Solution Approach 1:
The patent extracts and isolates the harmful parasitic capacitance effect by selectively coupling unselected memory blocks to ground through control switches during the precharge phase. This removes the harmful capacitive coupling from unselected blocks, allowing the selected memory block to be precharged without interference, thereby improving program speed while eliminating the harmful parasitic effect.
2Quantity of substance
If multiple memory blocks are vertically stacked to increase integration density, then the degree of integration is improved, but precharge operations become slower due to increased capacitance and leakage currents
Solution Approach 1:
The patent segments the memory block operations by introducing independent control switches for each memory block's source select lines. This segmentation allows selective grounding of unselected blocks during precharge operations, isolating their capacitance effects. As a result, vertically stacked memory blocks can maintain high integration density while individual blocks can be precharged independently and rapidly without being slowed by other blocks in the stack.
3Speed
If the precharge phase is optimized by grounding unselected memory blocks, then precharge speed is improved, but additional control circuitry is required
Solution Approach 1:
The control switches used to ground unselected memory blocks during precharge operations serve multiple functions: they act as grounding switches during precharge, as selection switches during program operations, and as isolation elements during verify phases. This multi-functionality allows the patent to achieve faster precharge speeds without proportionally increasing device complexity, as the same control circuitry performs multiple critical operations across different phases.
Data Source
AI summary
A semiconductor memory device, and a method of operating the same, includes a memory cell array, a peripheral circuit, and control logic. The memory cell array includes a plurality of memory blocks. The peripheral circuit is configured to perform a program operation on the memory cell array. The control logic is configured to control the program operation performed by the peripheral circuit. Each of the plurality of memory blocks is coupled to a drain select line, a plurality of word lines, and first and second source select lines that correspond to the memory block. During a program operation performed on a first memory block selected as a program target, among the plurality of memory blocks, the control logic controls the peripheral circuit so that a first source select line of a second memory block that is not selected as the program target, among the plurality of memory blocks, floats.