Semiconductor Memory Device Precharge Timing Control
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Solution Overview
Problem
In semiconductor memory devices, the degradation of word lines over time leads to overlapping timing between word line deactivation and bit line equalization signals, resulting in improper precharge operations and potential data loss.
Innovation Solution
A semiconductor memory device is designed with a control signal generation unit, word line control unit, and bit line equalization control unit to generate precharge signals with different activation durations, ensuring the bit line level equalization signal is activated earlier than the word line deactivation signal during a test operation, and adjusting the timing to prevent data failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the bit line level equalization signal is activated after the word line is completely disabled, then the precharge operation can be performed, but the timing may overlap when the word line is degraded, resulting in improper precharge operation
Solution Approach 1:
The patent applies preliminary action by activating the bit line level equalization signal before the word line is completely disabled. The control signal generation unit generates the bit line level equalization signal in advance, ensuring that the bit line precharge operation starts before the word line deactivation is complete. This prevents timing overlap and ensures proper precharge operation even when the word line is degraded.
2Reliability
If the word line deactivation timing is delayed to avoid overlap with bit line equalization, then precharge operation is safe, but the overall operation time increases
Solution Approach 1:
The patent uses preliminary action to activate the bit line level equalization signal before the word line deactivation is complete. This allows the precharge operation to start in advance, eliminating the need to delay word line deactivation for safety. As a result, data safety is maintained while the overall operation time is minimized.
3Reliability
If the bit line level equalization signal is activated earlier than word line deactivation, then timing margin is ensured, but data loss may occur if not properly controlled
Solution Approach 1:
The patent applies feedback by using the control signal generation unit to monitor and coordinate the timing between word line deactivation and bit line level equalization signal activation. The unit generates appropriate control signals based on the current state, ensuring that the bit line precharge operation starts at the correct moment and ends before the word line is fully deactivated. This feedback mechanism ensures timing margin while preventing data loss.
4Manufacturing precision
If separate control units are used for word line and bit line signals, then timing control is precise, but device complexity increases
Solution Approach 1:
The patent merges the control functions into a single control signal generation unit that handles both word line deactivation and bit line level equalization signal generation. This unified approach maintains timing control precision by coordinating both signals from one control source, while reducing device complexity compared to having separate control units for each function.
Data Source
AI summary
A semiconductor memory device may include a control signal generation unit suitable for generating a block selection signal in response to first and second precharge signals during a test operation; a word line control unit suitable for generating a word line deactivation signal in response to the first precharge signal and the block selection signal; and a bit line equalization control unit suitable for generating a bit line level equalization signal in response to the second precharge signal and the block selection signal.