Semiconductor Memory Precharge Timing Control
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Solution Overview
Problem
In semiconductor memory devices, precharging before a read operation can lead to precharge current concentration, which hinders high-speed read operations due to the simultaneous driving of sense amplifiers and peak current flow, necessitating independent timing for each sense amplifier and memory cell array.
Innovation Solution
A control circuit outputs separate signals for starting and completing precharging, with the start signal delayed through one or more delay circuits to each memory cell array, while the completion signal is not delayed, allowing precharging to be completed uniformly across arrays without depending on the start order, thereby avoiding precharge current concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If precharging is performed simultaneously for all memory cell arrays, then precharge current concentration occurs, but high-speed read operations cannot be performed
Solution Approach 1:
The patent divides the precharging operation into separate phases for different memory cell arrays. The control circuit generates different precharge timing signals for each array, allowing them to be charged at different times. This segmentation prevents current concentration while maintaining high-speed read capability.
Solution Approach 2:
The patent performs preliminary precharging actions for memory cell arrays before the read operation begins. By starting precharging in advance and completing it before the read cycle, the system prepares the bit lines without causing current peaks that would hinder high-speed operation.
2Power
If precharge timing is delayed for each memory cell array, then precharge current concentration is avoided, but completion of precharging is also delayed
Solution Approach 1:
The control circuit segments the precharging process by generating individual precharge timing signals for each memory cell array. This allows each array to be precharged at its optimal time without delaying the overall completion, as arrays can be charged in parallel across different time intervals.
Solution Approach 2:
The patent implements dynamic timing control where the precharge timing signals are adjusted based on the specific requirements of each memory cell array. The control circuit dynamically generates timing signals that optimize both current distribution and completion speed.
3Productivity
If sense amplifiers are driven simultaneously, then read operations can be performed in parallel, but power supply noise is generated and power supply voltage is reduced
Solution Approach 1:
The patent segments the sense amplifier driving into different time intervals. The control circuit generates different timing signals for sense amplifier activation based on the precharge completion status of each memory cell array. This prevents simultaneous driving and the associated power supply noise while maintaining parallel processing capability.
Solution Approach 2:
The patent performs preliminary precharging of memory cell arrays before activating sense amplifiers. By completing precharging in advance and using the completion signals to control sense amplifier timing, the system avoids simultaneous current draws that would cause power supply noise.
Data Source
AI summary
The semiconductor memory device includes a plurality of memory cell arrays and a control circuit that outputs a first signal and a second signal. The first signal instructs start of precharging of each memory cell array. The second signal instructs completion of the precharging and transition to a read access. The first signal is wired through one or more delay circuits to arrive at each memory cell array with a time difference, and the second signal is wired not through the one or more delay circuits.