Semiconductor Memory Device Precharge Timing for Program Disturb
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Solution Overview
Problem
Semiconductor memory devices face challenges in maintaining data reliability due to program disturb issues, where the precharge operation's effectiveness varies with the progression of program loops, affecting the channel potential and threshold voltage of memory cells.
Innovation Solution
The semiconductor memory device employs a write operation strategy with varying precharge times across program loops, extending the precharge time in later loops with higher program voltages to enhance channel potential and prevent program disturb, while optimizing the precharge time based on the progression of the write operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the precharge time is extended in later program loops with higher program voltages, then data reliability is improved by preventing program disturb, but writing time increases
Solution Approach 1:
The precharge time is dynamically adjusted based on the program loop progression and program voltage level. Specifically, the precharge time is extended in later program loops where higher program voltages are applied, while maintaining shorter precharge times in earlier loops. This dynamic adjustment optimizes the balance between preventing program disturb (improving reliability) and minimizing total write time.
Solution Approach 2:
The patent changes the precharge time parameter according to the program voltage level and loop progression. By varying this temporal parameter adaptively rather than using a fixed value, the system achieves improved data reliability in critical later loops while keeping overall write time acceptable through shorter precharge times in earlier loops.
2Stability of the object's composition
If the precharge time is extended to enhance channel potential, then threshold voltage stability is improved, but writing time increases
Solution Approach 1:
The precharge time is dynamically adjusted based on the program loop progression and program voltage level. Specifically, the precharge time is extended in later program loops where higher program voltages are applied, while maintaining shorter precharge times in earlier loops. This dynamic adjustment optimizes the balance between preventing program disturb (improving reliability) and minimizing total write time.
Solution Approach 2:
The patent changes the precharge time parameter according to the program voltage level and loop progression. By varying this temporal parameter adaptively rather than using a fixed value, the system achieves improved data reliability in critical later loops while keeping overall write time acceptable through shorter precharge times in earlier loops.
Data Source
AI summary
A semiconductor memory device includes first and second memory cells, first and second select transistors having first ends connected to the first and second memory cells, respectively, first and second bit lines connected to second ends of the first and second select transistors, respectively, and a select gate line connected to the first and second select transistors. A write operation includes first and second program loops. While a program pulse is being applied to a word line, a first voltage is applied to the first bit line, a second voltage to the second bit line, and a third voltage to the select gate line. Before the program pulse is applied to the word line, the second voltage is applied to the second bit line and a fourth voltage is applied to the select gate line for different time periods while in the first and second program loops, respectively.