Semiconductor Memory Standby Current Reduction via Precharge Circuit
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Solution Overview
Problem
Conventional semiconductor memory devices with cross-fail defects experience increased standby current due to unseparated defective word lines and bit lines, leading to standby failures, and existing solutions like pulsed equalizer control either allow voltage drift or require complex layouts and high active current dissipation.
Innovation Solution
A semiconductor memory device with a precharge circuit comprising a NMOS transistor and two PMOS transistors, controlled by specific logic-level control signals, where the NMOS transistor is turned off and PMOS transistors are turned on in standby mode to minimize standby current, and both are turned on briefly in active mode to precharge bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the repairing circuit has spare bit lines and word lines to replace defective lines, then the yield rate of the semiconductor memory device can be improved, but the space of the semiconductor memory device is increased
Solution Approach 1:
The patent merges the precharge function and equalization function into a single precharge circuit. The precharge circuit includes PMOS transistors for precharging bit lines and NMOS transistors for equalization, integrating multiple functions into one circuit block to save space while maintaining the ability to handle cross-fail defects through proper transistor control sequences
2Reliability
If the defective word lines and bit lines are not electrically separated, then the repairing circuit can remediate cross-fail, but the standby current increases causing standby failure
Solution Approach 1:
The patent employs dynamic control of transistor states during standby mode. The precharge circuit transistors (PMOS and NMOS) are controlled to be in specific on/off states during standby period, creating a high-impedance path that dynamically isolates the defective bit line and word line intersection, thereby reducing standby current while maintaining cross-fail remediation capability
Solution Approach 2:
The patent implements periodic precharge equalization cycles. During standby mode, the precharge circuit performs periodic equalization operations using controlled transistor switching, where NMOS transistors are activated to equalize bit line voltages and PMOS transistors are controlled to prevent current leakage through defective lines, reducing standby current through timed periodic action
3Loss of energy
If pulsed equalizer control is used while enabling the precharge equalizer signal, then current flow due to cross-fail can be minimized, but a floating state in each bit-line pair occurs causing bit-line voltage drift
Solution Approach 1:
The patent introduces a reference cell as an intermediary element for bit-line sensing. The reference cell provides a stable reference voltage that mediates the sensing operation, allowing the sensing amplifier to accurately detect bit line voltages even when using pulsed equalizer control, thereby preventing voltage drift while maintaining reduced current flow benefits
4Stability of the object's composition
If a reference cell is provided for bit-line sensing, then bit-line voltage drift can be avoided, but the layout becomes complicated, control becomes difficult, and active current dissipation increases
Solution Approach 1:
The patent makes the precharge circuit multi-functional by integrating both precharge and equalization functions into a single circuit block. The precharge circuit uses PMOS transistors for precharging and NMOS transistors for equalization, controlled by different control signals. This universal circuit eliminates the need for separate reference cells and dedicated equalization circuits, reducing layout complexity and current dissipation while maintaining voltage stability
Data Source
AI summary
A semiconductor memory device includes memory cells, a sensing amplifier, a precharge circuit, and a control signal generator. The precharge circuit has a NMOS transistor and two PMOS transistors, and is used to precharge bit lines of a bit line pair, wherein the NMOS transistor is controlled by a first control signal, and the two PMOS transistors are controlled by a second control signal. The control signal generator is used to generate the first and second control signals, wherein the first control signal is at a logic high level only when the second control signal is at a first logic low level, the first control signal is at a logic low level when the second control signal is at a second logic low or a first logic high level, and the second logic low level is higher than the first logic low level.