3D Memory Device Precharge Voltage Control for Program Disturbance
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Solution Overview
Problem
3-dimensional semiconductor memory devices face limitations in integration density and program disturbance due to varying channel boosting levels between different memory cell groups, which affect the efficiency of program operations.
Innovation Solution
A semiconductor memory device with a memory cell array comprising a first and second memory cell group, where a voltage generator produces distinct precharge voltages for each group, and a controller applies these voltages to mitigate channel boosting level differences, thereby reducing program disturbance during operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single precharge voltage is applied to all memory cell groups during program operation, then the device structure remains simple, but channel boosting level differences cause program disturbance in different memory cell groups
Solution Approach 1:
The memory cell array is divided into multiple memory cell groups (first memory cell group and second memory cell group), and each group is assigned a dedicated precharge voltage (first precharge voltage and second precharge voltage). This segmentation allows independent voltage control for each group, enabling tailored precharge levels that compensate for position-dependent channel boosting effects without requiring complex global voltage adjustment mechanisms.
Solution Approach 2:
Different precharge voltages are applied to different memory cell groups based on their specific positions and channel boosting characteristics. The first memory cell group receives a first precharge voltage while the second memory cell group receives a second precharge voltage, creating local quality variations that optimize program operation for each group's specific conditions rather than using a uniform approach.
2Reliability
If multiple precharge voltages are generated for different memory cell groups, then program disturbance is reduced, but the voltage generation circuit complexity increases
Solution Approach 1:
The voltage generator is segmented into multiple independent voltage generation paths, with each path dedicated to generating a specific precharge voltage for a particular memory cell group. This modular segmentation allows each voltage path to be optimized independently while maintaining overall system reliability, and the segmented structure makes the complexity manageable through functional decomposition.
3Quantity of substance
If uniform precharge voltage is used across all strings, then the control logic remains simple, but integration density improvement is limited due to program disturbance
Solution Approach 1:
The control logic is segmented to independently manage precharge voltages for different memory cell groups. The controller generates and applies distinct precharge voltages (first precharge voltage for first memory cell group, second precharge voltage for second memory cell group) based on the target string position, enabling high integration density through vertical stacking while maintaining program operation reliability through position-aware voltage control.
Solution Approach 2:
The control system implements local quality by applying different precharge voltage levels to different memory cell groups based on their specific positions in the vertical stack. This local optimization allows the system to achieve high integration density through 3D stacking while compensating for position-dependent effects that would otherwise limit reliable operation.
Data Source
AI summary
Provided are a semiconductor memory device and an operating method thereof. The semiconductor memory device includes a memory cell array including a plurality of strings, wherein each of the plurality of strings includes a first memory cell group, and a second memory cell group and peripheral circuits configured to generate a first precharge voltage applied to the first memory cell group and a second precharge voltage applied to the second memory cell group when a channel precharge operation is performed during a program operation, and generate a program voltage to apply the program voltage to the memory cell array when a program voltage application is performed.