Memory Circuit Pre-Decoding With Local Repeaters for Faster Address Setup
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, the resistance of conductive lines within these digital devices affects operating voltages and overall IC performance, leading to challenges in timing improvements and address setup time.
Innovation Solution
The implementation of a memory circuit with a global control circuit generating pre-decoder signals and local control circuits with repeater circuits that increase the driving strength of local pre-decoder signals, improving timing by generating local versions of global pre-decoder signals to enhance address setup time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If IC size is reduced to improve integration, then device complexity increases, but conductive line resistance increases affecting operating voltages and timing performance
Solution Approach 1:
The address signal path is segmented into global pre-decoder signals distributed across multiple local control circuits, each generating local pre-decoder signals. This segmentation reduces the effective distance signals must travel through conductive lines, mitigating resistance effects in smaller ICs while maintaining functional integrity.
Solution Approach 2:
Repeater circuits are introduced as intermediary elements between global pre-decoder signals and local pre-decoder signals. These repeaters amplify and regenerate signals, compensating for voltage drops caused by increased conductive line resistance in miniaturized ICs, thereby maintaining timing performance.
2Loss of time
If global pre-decoder signals are distributed to local control circuits, then address setup time is improved, but signal driving strength decreases due to resistance
Solution Approach 1:
Global pre-decoder signals are generated and distributed in advance to multiple local control circuits before the actual memory access operation. This preliminary distribution allows local circuits to prepare local pre-decoder signals early, reducing critical path delay and improving address setup time while maintaining signal strength through repeater circuits.
Solution Approach 2:
Each local control circuit is equipped with its own repeater circuits that provide localized signal amplification. This local quality enhancement ensures that each local pre-decoder signal maintains sufficient driving strength for its specific region, compensating for resistance effects without requiring increased global signal power.
Data Source
AI summary
A memory circuit includes a global control circuit, a first local control circuit, and a first set of word line post-decoder circuits coupled to a first set of memory cells that is configured to store a first set of data. The global control circuit is configured to generate a first and second set of global pre-decoder signals, and a first set of local address signals. The first local control circuit includes a first set of repeater circuits and a first clock pre-decoder circuit. The first set of repeater circuits is configured to generate a first and second set of local pre-decoder signals in response to the corresponding first and second set of global pre-decoder signals. The first clock pre-decoder circuit is configured to generate a first and second set of clock signals in response to the first set of local address signals and the first clock signal.