Memory Pre-Decoder Biasing for Low-Power Polarity Switching
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Solution Overview
Problem
Existing memory devices with 1P1N bi-polar decoders exhibit high power consumption due to changes in gate biases during polarity transitions, which affects the efficiency of selection and de-selection signals for resistance variable memory cells.
Innovation Solution
The use of 1P2N bi-polar decoders, comprising one p-type transistor and two n-type transistors, which maintain constant gate biases during polarity transitions, reducing power consumption and providing eight configuration modes for selection and de-selection signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If 1P1N bi-polar decoders are used, then selection and de-selection signals can be provided for memory cells, but power consumption is high due to changes in gate biases during polarity transitions
Solution Approach 1:
The patent changes the biasing parameters of the decoder circuit by transitioning from 1P1N to 1P2N configuration. Specifically, it maintains constant gate biases during polarity transitions by using two n-type transistors instead of one, thereby reducing power consumption while handling the same memory cell selection task
Solution Approach 2:
The patent segments the decoder circuit into one p-type transistor and two n-type transistors (1P2N configuration). This segmentation allows independent control of bias conditions for each transistor, enabling constant gate bias maintenance during polarity transitions and thus reducing power consumption
2Loss of energy
If 1P2N bi-polar decoders are used, then power consumption is reduced by maintaining constant gate biases, but device complexity increases
Solution Approach 1:
The 1P2N decoder circuit is designed to automatically maintain constant gate biases during polarity transitions without requiring external intervention. The circuit self-regulates the bias conditions through its inherent transistor configuration, reducing power consumption while managing the increased complexity internally
3Ease of operation
If gate biases change during polarity transitions, then selection signals can be provided, but power consumption increases
Solution Approach 1:
The patent implements dynamic bias management where the gate biases are maintained constant during polarity transitions through the 1P2N configuration. This dynamic approach allows the circuit to adapt to polarity changes while keeping power consumption low, as the bias conditions do not need to be re-established during transitions
Data Source
AI summary
The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a p-type transistor having a first gate, a first n-type transistor having a second gate, and a second n-type transistor having a third gate, and pre-decoder circuitry configured to provide a bias condition for the first gate, the second gate, and the third gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises zero volts for the first gate, the second gate, and the third gate for a positive configuration for the memory cells and a negative voltage for the third gate and zero volts for the first gate and the second gate for a negative configuration for the memory cells.