Memory Pre-Decoder Biasing for Low-Power Polarity Switching
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Solution Overview
Problem
Existing memory devices utilizing 1P1N bi-polar decoders for resistance variable memory cells exhibit high power consumption due to significant changes in gate biases during polarity transitions, which is inefficient.
Innovation Solution
Implementing decoder circuitry with one p-type transistor and two n-type transistors (1P2N bi-polar decoders) to provide selection and de-selection signals, which reduces power consumption by maintaining stable gate biases during polarity transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If 1P1N bi-polar decoders are used for resistance variable memory cells, then the memory device can provide selection and de-selection signals, but the gate biases change significantly during polarity transitions causing high power consumption
Solution Approach 1:
The decoder is segmented into three separate transistor components: one p-type transistor and two n-type transistors. This segmentation allows independent control of gate biases for each transistor, enabling the p-type transistor gate to maintain a stable first bias and the n-type transistor gates to maintain stable second and third biases during polarity transitions, thereby reducing power consumption while maintaining proper selection and de-selection functionality
Solution Approach 2:
The invention changes the bias parameters from dynamic (changing during polarity transitions) to static (stable during operation). By setting the p-type transistor gate bias to a stable first bias and the n-type transistor gates to stable second and third biases, the system eliminates the significant gate bias changes that occur in conventional 1P1N decoders during polarity transitions, directly reducing power consumption
2Use of energy by stationary object
If 1P1N bi-polar decoders are used, then the device structure is simpler, but power consumption increases due to gate bias changes during polarity transitions
Solution Approach 1:
The decoder is segmented into three separate transistor components: one p-type transistor and two n-type transistors. This segmentation allows independent control of gate biases for each transistor, enabling the p-type transistor gate to maintain a stable first bias and the n-type transistor gates to maintain stable second and third biases during polarity transitions, thereby reducing power consumption while maintaining proper selection and de-selection functionality
Solution Approach 2:
The invention changes the bias parameters from dynamic (changing during polarity transitions) to static (stable during operation). By setting the p-type transistor gate bias to a stable first bias and the n-type transistor gates to stable second and third biases, the system eliminates the significant gate bias changes that occur in conventional 1P1N decoders during polarity transitions, directly reducing power consumption
Data Source
AI summary
The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a p-type transistor having a first gate, a first n-type transistor having a second gate, and a second n-type transistor having a third gate, and pre-decoder circuitry configured to provide a bias condition for the first gate, the second gate, and the third gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises zero volts for the first gate, the second gate, and the third gate for a positive configuration for the memory cells and a negative voltage for the third gate and zero volts for the first gate and the second gate for a negative configuration for the memory cells.