Memory Access Prediction Unit for Multi-Stage Data Processing
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Solution Overview
Problem
The existing memory access mechanisms in data processing systems are inefficient and power-consuming due to the time-consuming and power-intensive process of retrieving data from multiple memory layers, which reduces overall system performance and efficiency.
Innovation Solution
A method and apparatus for predicting memory access are introduced, where data processing is performed in multiple stages with segment processing, dividing memory into blocks and using a prediction unit to generate a predicting value for accessing memory blocks, and a determining unit to verify the correctness of the prediction, thereby optimizing memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is retrieved from multiple memory layers (cache memory and outer memory), then data storage capacity is sufficient, but access time increases and power consumption increases
Solution Approach 1:
The patent applies preliminary action by predicting future memory access addresses before actual access occurs. The prediction unit generates predicted addresses in advance, allowing the system to proactively prepare for upcoming memory operations rather than reactively responding to access requests, thereby reducing access time
Solution Approach 2:
The patent segments the memory access process into distinct phases: prediction phase (generating predicted addresses), verification phase (comparing predicted vs. actual addresses), and execution phase (actual memory access). This segmentation allows each phase to be optimized independently and enables parallel processing of multiple predictions
2Quantity of substance
If data is retrieved from multiple memory layers (cache memory and outer memory), then data storage capacity is sufficient, but power consumption increases
Solution Approach 1:
By performing address prediction in advance, the system identifies which memory blocks will be accessed beforehand. This allows power management circuits to selectively activate only the necessary memory blocks and associated access circuits, rather than powering up entire memory layers, thereby reducing overall power consumption
Solution Approach 2:
The patent extracts and isolates the prediction function into a separate prediction unit that operates independently from the main memory access path. This extraction allows the prediction logic to be implemented with minimal power consumption while providing significant energy savings by preventing unnecessary memory access operations
3Measurement precision
If address calculation and memory search are performed sequentially, then address accuracy is maintained, but processing efficiency decreases
Solution Approach 1:
The prediction unit performs address prediction in parallel with ongoing memory operations. Multiple predicted addresses are generated simultaneously rather than sequentially, and the verification unit compares multiple predictions against actual addresses in parallel, thereby maintaining accuracy while dramatically improving processing throughput
Solution Approach 2:
The patent implements a feedback mechanism where the results of actual memory accesses are fed back to the prediction unit. This feedback allows the prediction logic to learn from actual access patterns and improve future predictions, maintaining high accuracy while enabling faster parallel processing of multiple address predictions
Data Source
AI summary
A method for predicting memory access, where each data processing procedure is performed in a plurality of stages with segment processing, and the plurality of stages include at least a first stage and a second stage, includes: dividing a memory into a plurality of memory blocks, generating a predicting value of a second position information according to a correct value of a first position information at the first stage, accessing the memory blocks of the corresponding position in the memory according to the predicting value of the second position information, and identifying whether the predicting value of the second position information is correct or not for determining whether the memory is re-accessed, where the first stage occurs before the second stage in a same data processing procedure.