Memory Device Prefetch Latch for Fast Cross Row Data Access

Solution Overview

Problem

Conventional memory devices experience latency when performing burst accesses that span across rows or array boundaries, leading to delays in data access speeds.

Innovation Solution

The implementation of a memory device with a prefetch latch and modified row and column select circuits that allow simultaneous or sequential activation of word lines across row or array boundaries, enabling data to be prefetched and stored in a latch, thereby eliminating additional latency during burst operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a burst access spans across row boundaries in a conventional memory device, then data can be accessed sequentially, but additional latency is introduced due to row switching operations

Engineering Contradiction:

Improvedata access speedVSAvoidlatency during row crossing

Core Design Contradiction:

SpeedVSLoss of time

Solution Approach 1:

The patent applies preliminary action by activating the next word line (WL(n+1)) in advance before the current row (ROWn) is fully accessed. This allows the memory device to prepare the next row for access while still reading from the current row, thereby eliminating the latency that would otherwise occur when switching between rows during a burst access operation.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent ensures continuity of useful action by overlapping the access operations of two consecutive rows. While data is being read from ROWn, the next word line WL(n+1) is already activated and prepared, so that when the burst access needs to transition to the next row, the switching operation is already complete or occurs simultaneously, maintaining continuous data flow without interruption.

Inventive Principle:

Principle #20Continuity of useful action

2Adaptability or versatility

If conventional memory devices perform row switching during burst access, then sequential data access is enabled, but access speed decreases due to precharge and decode cycles

Engineering Contradiction:

Improveburst access capabilityVSAvoidaccess speed during row switching

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent applies preliminary action by activating the next word line (WL(n+1)) in advance before the current row (ROWn) is fully accessed. This allows the memory device to prepare the next row for access while still reading from the current row, thereby eliminating the latency that would otherwise occur when switching between rows during a burst access operation.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent ensures continuity of useful action by overlapping the access operations of two consecutive rows. While data is being read from ROWn, the next word line WL(n+1) is already activated and prepared, so that when the burst access needs to transition to the next row, the switching operation is already complete or occurs simultaneously, maintaining continuous data flow without interruption.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS7660167B1Memory device and method for fast cross row data access

Publication Date: 2010.02.09 MONTEREY RESEARCH LLC

AI summary

A memory device can provide burst access to row boundary crossing addresses without introducing inter-burst latency. Address locations for a first row of the burst can be accessed at speed, while a prefetch latch can be accessed in lieu of a next row.