Multi-tiered Memory Prefetching via Pattern History Extraction
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Solution Overview
Problem
Existing data prefetching methods in multi-core processors face challenges with large pattern history tables that consume processor chip space and suffer from hash aliasing issues, leading to inefficient data retrieval from system memory.
Innovation Solution
Implementing a multi-tiered system memory with a near memory cache that stores frequently accessed data, reducing access times and eliminating hash aliasing by using a faster, volatile near memory as a cache for emerging non-volatile technologies, which acts as a high-priority region of system memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large pattern history table structure is used to store data access patterns, then data prefetching capability is improved, but processor chip space is consumed and hash aliasing problems occur
Solution Approach 1:
The patent extracts the pattern history table from the processor chip and places it in system memory, eliminating the need for large on-chip storage while maintaining prefetching capability. The processor chip now only contains the prefetcher logic and a small portion of the pattern history table, while the bulk of the table resides in system memory and is accessed as needed.
Solution Approach 2:
The patent introduces an intermediary structure where a small portion of the pattern history table is kept on the processor chip and the majority is stored in system memory. This intermediary arrangement allows the processor to maintain prefetching functionality while offloading the storage burden to system memory, effectively resolving the space constraint.
2Productivity
If a large pattern history table structure is used to store data access patterns, then data prefetching capability is improved, but hash aliasing problems occur
Solution Approach 1:
The patent segments the pattern history table into two parts: a small, frequently accessed portion stored on the processor chip, and a large, less frequently accessed portion stored in system memory. This segmentation allows the critical prefetching data to be quickly accessible while reducing the overall hash aliasing impact by distributing the table entries across different memory locations.
3Loss of time
If data is retrieved from system memory, then data retrieval time is reduced by using last level cache, but system memory access time remains significantly longer compared to cache access
Solution Approach 1:
The patent implements preliminary action by using the prefetcher logic to predict future data access patterns and load data into the last level cache before it is actually needed by the processor cores. This advance preparation reduces the impact of slow system memory access by ensuring that frequently accessed data is already in the faster cache when needed.
Data Source
AI summary
A method is described that includes creating a first data pattern access record for a region of system memory in response to a cache miss at a host side cache for a first memory access request. The first memory access request specifies an address within the region of system memory. The method includes fetching a previously existing data access pattern record for the region from the system memory in response to the cache miss. The previously existing data access pattern record identifies blocks of data within the region that have been previously accessed. The method includes pre-fetching the blocks from the system memory and storing the blocks in the cache.