Memory Preprocessing Queue Control for Lower Storage Latency
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Solution Overview
Problem
Existing memory devices and storage devices face challenges in reducing latency due to the lack of efficient preprocessing tasks before main operations, leading to suboptimal performance.
Innovation Solution
Implementing a memory device with a main core and subcores that perform preprocessing tasks in response to preprocessing commands, and a controller that queues and manages these tasks through a semaphore manager to optimize operation sequencing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If preprocessing tasks are performed before main operations, then operation latency is reduced, but device complexity increases due to additional main core and subcore architecture
Solution Approach 1:
The processing architecture is segmented into a main core and multiple subcores. The main core handles preprocessing tasks while subcores handle main operations, allowing parallel execution of different task types. This segmentation enables preprocessing to occur independently before main operations without blocking the overall workflow, thereby reducing operation latency while maintaining manageable complexity through clear functional division.
Solution Approach 2:
Preprocessing tasks are performed in advance before the main operation commands are executed. The main core executes preprocessing commands to prepare data and resources beforehand, so that when subcores receive main operation commands, the preparatory work is already complete. This preliminary action reduces the critical path latency of main operations while the modular architecture keeps complexity controlled.
2Productivity
If parallel processing of preprocessing and main tasks is implemented, then productivity is improved, but control complexity increases due to semaphore management
Solution Approach 1:
A semaphore manager is introduced as an intermediary component that mediates between the main core and subcores. The semaphore manager receives preprocessing commands from the main core, manages the execution state of subcores, and coordinates the transition between preprocessing and main operations. This intermediary simplifies the control complexity by centralizing the synchronization logic, allowing parallel processing to proceed efficiently without requiring complex direct coordination between all processing units.
Solution Approach 2:
The semaphore manager implements feedback mechanisms by monitoring the execution state of subcores and adjusting command distribution accordingly. When subcores complete preprocessing tasks or are ready for main operations, the semaphore manager receives feedback and dynamically manages the flow of commands. This feedback-based control enables efficient parallel processing while keeping the control mechanism manageable through state-aware resource allocation.
3Speed
If multiple subcores are used for task execution, then operation speed is increased, but manufacturing complexity increases
Solution Approach 1:
Multiple subcores are designed with universal functionality to execute both preprocessing tasks and main operations. Each subcore can be dynamically assigned different task types based on system needs, rather than being dedicated to a single function. This multi-functionality increases task execution speed through parallel processing while simplifying manufacturing, as identical or near-identical subcore units can be produced using the same manufacturing processes, reducing the complexity of producing different specialized components.
Data Source
AI summary
A memory device may include a plurality of subcores and a main core configured to control a subcore of the plurality of subcores to perform a preprocessing task of a memory operation in response to a preprocessing command.