Memory System Pre-Program Voltage Adjustment for Deep Erase
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Solution Overview
Problem
Nonvolatile memory systems face challenges with deep erase phenomena, leading to retention issues and uncorrectable errors due to the influence of adjacent memory cells, which affect the reliability and performance of memory operations.
Innovation Solution
A memory system that includes a controller and a nonvolatile memory device with a peripheral circuit capable of applying check voltages to determine status information and variably adjusting program start voltages based on the number of fail bits, using an incremental step pulse program scheme to prevent deep erase phenomena through pre-program operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional erase operation is performed on a memory block, then the memory block can be reused, but deep erase phenomena occur causing retention issues and uncorrectable errors
Solution Approach 1:
The patent applies preliminary action by performing a pre-program operation before the conventional erase operation. This pre-program operation involves applying program voltages to memory cells in the target memory block to establish a known initial state, which then serves as a reference for detecting and correcting deep erase phenomena during the subsequent erase operation. This preliminary preparation enables the system to identify and mitigate retention issues before they cause uncorrectable errors.
2Productivity
If adjacent memory cells are erased, then the memory block can be cleaned, but retention issues and uncorrectable errors occur due to influence from adjacent cells
Solution Approach 1:
The patent applies local quality by detecting the specific state of each memory cell or group of memory cells within the target memory block using check data acquisition. Based on this local detection, the system determines status information that identifies which cells require special handling during the erase operation. This localized approach allows the system to address retention issues in specific areas affected by adjacent cell erasure while maintaining efficient cleaning of the entire block.
Solution Approach 2:
The patent implements feedback by acquiring check data from the memory block before the erase operation and using this information to determine status information about the memory cells. This feedback loop enables the system to adapt the erase operation parameters based on the actual state of the memory block, allowing for correction of deep erase phenomena and reduction of uncorrectable errors caused by adjacent cell influence.
3Ease of operation
If a fixed program voltage is applied to all memory blocks, then the operation is simple, but deep erase phenomena cannot be prevented
Solution Approach 1:
The patent applies dynamics by making the program voltage variable rather than fixed. The controller determines status information based on check data and uses this information to dynamically adjust the program voltage applied during the pre-program operation. This dynamic voltage adjustment allows the system to prevent deep erase phenomena in memory blocks that are more susceptible to retention issues, while maintaining operational simplicity through automated control based on detected status.
Data Source
AI summary
A memory system may include a memory cell array including a plurality of memory blocks; a peripheral circuit configured to apply a check voltage for acquiring check data to a target memory block and apply program voltages to the target memory block in a pre-program operation for the target memory block; and a controller configured to control the peripheral circuit, determine status information on the target memory block based on the check data, and variably apply a program start voltage to the target memory block based on the status information in the pre-program operation.