Nonvolatile Memory Write Loop Omitting Preverify Step
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Solution Overview
Problem
The Quick Pass Write method for nonvolatile semiconductor storage devices lengthens processing time due to the increased number of detection operations required in the verify operation, which can be inefficient for memory cells with slow program speeds.
Innovation Solution
The proposed solution involves omitting the preverify step for memory cells with slow program speeds, determining this by the number of write loops, and adjusting the write sequence to reduce processing time while maintaining the effectiveness of the Quick Pass Write method.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the preverify step is performed for all memory cells using the Quick Pass Write method, then the threshold voltage distribution is prevented from being widened, but the processing time is lengthened
Solution Approach 1:
The patent applies local quality by differentiating the verify operation based on memory cell characteristics. Memory cells are divided into two groups: those requiring preverify steps (first memory cell group) and those that do not (second memory cell group). This allows the preverify step to be selectively applied only where necessary to maintain threshold voltage distribution, rather than uniformly applied to all cells, thereby reducing overall processing time while preserving precision where needed.
Solution Approach 2:
The patent implements partial action by performing the preverify step only for a portion of memory cells (those in the first group with slower program speeds) rather than all memory cells. This partial application of the preverify operation maintains the necessary control over threshold voltage distribution for critical cells while avoiding redundant operations on cells that reach target voltage faster, thus optimizing the balance between precision and time efficiency.
2Loss of time
If the preverify step is omitted to reduce processing time, then the processing time is shortened, but the threshold voltage distribution may be broadened
Solution Approach 1:
The patent applies local quality by differentiating the verify operation based on memory cell characteristics. Memory cells are divided into two groups: those requiring preverify steps (first memory cell group) and those that do not (second memory cell group). This allows the preverify step to be selectively applied only where necessary to maintain threshold voltage distribution, rather than uniformly applied to all cells, thereby reducing overall processing time while preserving precision where needed.
Solution Approach 2:
The patent implements feedback by using detection operations to monitor the program speed of memory cells and dynamically determining which cells require preverify steps. The control circuit receives feedback from the detection operation results and adjusts the verify operation accordingly, ensuring that preverify is applied only to cells that need it, thus maintaining threshold voltage distribution precision while minimizing processing time.
Data Source
AI summary
A nonvolatile semiconductor storage device according to an embodiment includes: a memory cell array including plural memory cells; and a control circuit that repeatedly performs a write loop including a program operation and a verify operation in data write performed to the memory cell, the verify operation including a preverify step to check whether a threshold voltage of the memory cell transitions to a preverify voltage, and a real verify step to check whether the threshold voltage of the memory cell transitions to the real verify voltage, the write loop including one or at least two verify operations corresponding to pieces of the data, the control circuit performing the write loop in which the preverify step of the verify operation corresponding to a first data is omitted after obtaining a first condition.