Memory Processing Modules with Segmented Memory Banks
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Solution Overview
Problem
Current processing systems, such as CPUs and GPUs, face bottlenecks due to shared memory architectures, leading to lower effective processing speeds and increased power consumption as the clock speeds exceed data transfer speeds across memory buses.
Innovation Solution
The implementation of memory processing modules (MPMs) with processing units paired directly with memory banks on the same semiconductor die, allowing for local processing and reducing reliance on shared memory buses, and the use of hash tables with optimized parameters to minimize overflow risks and enhance key-value processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If shared memory architecture is used to enable parallel processing, then processing capability is improved, but data transfer speed becomes a bottleneck due to memory bus limitations
Solution Approach 1:
The patent divides the monolithic shared memory architecture into multiple independent memory banks, each with its own interface. This segmentation allows multiple processing units to access different memory banks simultaneously, eliminating the bottleneck of a single shared memory bus and enabling parallel data transfer operations.
Solution Approach 2:
The patent transitions from a single-dimension shared memory bus to a multi-dimensional memory bank structure where processing units can access memory through multiple independent paths. This dimensional expansion allows concurrent access patterns that were impossible in the original shared memory architecture.
2Speed
If clock speed is increased to improve processing speed, then processing speed is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic clock gating for individual memory banks, allowing the clock signal to be enabled only when a memory bank is actively being accessed. This dynamic control reduces unnecessary clock cycling and associated power consumption while maintaining high processing speeds during active operations.
Solution Approach 2:
The patent applies different clocking strategies to different memory banks based on their access patterns. Frequently accessed memory banks can maintain higher clock speeds, while less accessed banks can operate at lower speeds or be clock-gated, optimizing the overall power-performance balance locally for each bank.
3Productivity
If hash table utilization is increased to improve memory efficiency, then memory efficiency is improved, but overflow risk increases
Solution Approach 1:
The patent performs preliminary analysis of the data distribution characteristics before constructing the hash table. By pre-calculating the expected key distribution and potential collision patterns, the system can determine optimal table size and bucket configuration that guarantees sufficient capacity while maximizing memory efficiency, preventing overflow before it occurs.
Solution Approach 2:
The patent dynamically adjusts hash table parameters such as table size, number of buckets, and bucket capacity based on the actual data characteristics. By changing these parameters to match the specific workload, the system achieves high memory efficiency while maintaining overflow protection through statistically guaranteed capacity margins.
Data Source
AI summary
A microprocessor includes a function-specific architecture, an interface configured to communicate with an external memory via at least one memory channel, a first architecture block configured to perform a first task associated with a thread, and a second architecture block configured to perform a second task associated with the thread. The second task includes a memory access via the at least one memory channel. The microprocessor further includes a third architecture block configured to perform a third task associated with the thread. The first architecture block, the second architecture block, and the third architecture block are configured to operate in parallel such that the first task, the second task, and the third task are all completed during a single clock cycle associated with the microprocessor.