Memory Processing Unit Dot Product Computation
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Solution Overview
Problem
Conventional computing systems experience significant processing latency and power consumption due to the time-consuming transfer of large data sets between memory and processing units.
Innovation Solution
A memory device architecture that performs matrix dot product calculations within the memory itself, utilizing an array of memory cells, input registers, word line drivers, readout circuitry, accumulators, and shift registers to efficiently compute dot products by sequentially biasing word lines and accumulating partial products, thereby reducing the need for data transfer to a central processing unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred from memory to processing units for computation, then computation can be performed, but processing latency and data transfer latency increase
Solution Approach 1:
The patent merges memory and processing functions into a single integrated device. Memory cells store data while integrated circuits perform computations directly on the stored data, eliminating the need for separate data transfer between distinct memory and processing units. This combination resolves the latency issue by making the processing unit co-located with the memory.
Solution Approach 2:
The memory device is designed to perform multiple functions: it can store data in memory cells and simultaneously perform computational operations on that data using integrated circuits. This multi-functionality allows the same hardware structure to serve both as memory and as a processing unit, reducing the need for data movement between specialized components.
2Productivity
If data is transferred between memory and processing units, then computation can be performed, but power consumption increases
Solution Approach 1:
By combining memory storage and computation capabilities into a single integrated device, the patent eliminates the energy-consuming data transfer process between separate memory and processing units. The integrated circuits perform computations directly on data residing in the memory cells, significantly reducing power consumption associated with data movement.
3Reliability
If conventional memory-processor architecture is used, then data can be stored and processed, but processing latency increases
Solution Approach 1:
The patent keeps data in the memory cells in a ready state, with integrated circuits positioned to immediately perform computations on the stored data. This preliminary positioning of both data and processing capability eliminates the need for data transfer latency, allowing computations to begin almost immediately after data is stored or made accessible.
Data Source
AI summary
A memory processing unit can be configured to compute partial products between one or more elements of a first matrix stored in a given row of a memory cell array and sequential bits of one or more elements of a second matrix. The partial products can be calculated first sequentially across the set of rows and second sequentially across the bit positions of the elements of the second matrix. Alternatively, the partial products can be calculated first sequentially across the bit positions of the elements of the second matrix first and second sequentially across the set of rows. The partial products for each column of elements can be accumulated and bit shifted to compute the dot product of the first and second matrix.