Memory Processing Unit Zero Bit Skipping Logic
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Solution Overview
Problem
Conventional computing systems face challenges in reducing processing latency, data transfer latency, and power consumption due to the time-consuming transfer of large data sets between memory and processing units.
Innovation Solution
The implementation of a memory device with bit skipping logic and masking logic that selectively processes non-zero bit positions in matrix dot product computations, reducing unnecessary calculations and energy consumption by skipping zero bit values and conditionally accessing rows based on bit values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If data is transferred from memory to processing units for calculation, then processing can be performed, but data transfer latency and power consumption increase
Solution Approach 1:
The patent merges memory storage and processing functions into a single memory device. The memory device includes storage locations for multipliers and multiplicands, bit skipping logic for optimization, readout circuitry for sensing, and accumulators for computing dot products. This integration eliminates the need for separate data transfer between memory and processing units, thereby reducing data transfer latency and power consumption while enabling direct computation within the memory device.
2Productivity
If all bit positions are processed in matrix dot product computations, then complete calculation is achieved, but processing time and energy consumption increase due to zero bit values
Solution Approach 1:
The patent implements bit skipping logic that identifies and skips zero bit positions in the multiplicand during matrix dot product computations. The bit skipping logic determines which bit positions contain non-zero values and selectively activates readout circuitry only for those positions. This skipping mechanism reduces the number of processing operations required, thereby increasing throughput while decreasing energy consumption by avoiding unnecessary processing of zero values.
Solution Approach 2:
The patent employs dynamic row activation where the readout circuitry sequentially biases and senses rows of the first storage location based on the bit positions identified as non-zero by the bit skipping logic. This dynamic approach adapts the processing activity to the actual data characteristics, activating only the necessary computational paths and skipping inactive ones, thus optimizing both throughput and energy efficiency.
Data Source
AI summary
A memory processing unit can be configured to compute partial products between one or more elements of a first matrix stored in a first storage location and sequential bits of one or more elements of a second matrix stored in a second storage location. The partial products can be calculated utilizing zero bit skipping to increase throughput and or reduce energy consumption. The partial products for each column of elements can be accumulated and bit shifted to compute the dot product of the first and second matrix.