In-Memory Processor Mesh for Low-Power Neural Network Computing

The patent merges memory and processing elements into a unified architecture where processing elements directly access and manipulate data stored in memory cells without requiring separate data movement operations. This integration eliminates the power-consuming data transfer between distinct memory and processing units while maintaining high computation throughput through in-memory computing operations.

The patent transitions from traditional von Neumann architecture to a two-dimensional mesh architecture where processing elements are arranged in a grid and each element can directly access neighboring memory cells. This spatial reorganization enables parallel data access and computation across multiple dimensions, reducing the need for sequential data movement and lowering overall power consumption while increasing computational capacity.

The patent divides the computing system into multiple small processing elements arranged in a two-dimensional mesh, where each element handles a portion of the overall computation. This segmentation allows the system to achieve high computation capacity through parallel processing of many small units rather than requiring fewer large processing elements, optimizing the area-to-computation ratio.

Each processing element in the mesh architecture is designed to be universal and multi-functional, capable of performing various computational operations and communicating with multiple neighbors. This universality allows the same hardware structure to handle different deep learning workloads efficiently, maximizing computation capacity without proportionally increasing chip area.