Memory Processor Multiprocessing Architecture for Large Dataset Computing
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Solution Overview
Problem
Current processor architectures face limitations in enhancing computing speed due to small cache sizes, low cache hit rates, and memory access time constraints, especially when handling large datasets for intensive computations like neural networks or genome sequencing, and existing methods like FPGA or GPU architectures increase energy consumption with more processing circuits.
Innovation Solution
A memory processor-based multiprocessing architecture with a main processor and multiple memory chips, where each memory chip has processing units and data storage areas, utilizing a data index mechanism to assign computing tasks and communicate through dedicated channels, allowing for efficient distribution and processing of large datasets across multiple processing units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of processing circuits is increased to enhance computing speed, then computing performance is improved, but energy consumption is increased
Solution Approach 1:
The patent merges processing units with memory units into integrated memory chips, where each memory chip contains both processing units and data storage areas. This integration allows data to be processed directly within the memory chip without being transferred to separate processing circuits, thereby improving computing speed while reducing energy consumption associated with data transfer and the overhead of additional processing circuits.
Solution Approach 2:
The patent segments the computing system into multiple memory chips, each containing processing units and data storage areas. This segmentation distributes the computational workload across multiple integrated units, improving overall computing performance while maintaining energy efficiency through localized processing within each chip segment.
2Productivity
If a field programmable gate array (FPGA) architecture or application-specific integrated circuit (ASIC) architecture is used to share computing tasks, then computing speed is enhanced, but memory access time limit cannot be overcome
Solution Approach 1:
The patent combines processing units and memory storage areas into a single integrated memory chip structure. This merging eliminates the need for separate memory access operations to external memory, as data can be directly accessed and processed within the same chip. This significantly reduces memory access time while maintaining enhanced computing speed through the distributed processing architecture.
3Productivity
If a graphics processing unit (GPU) architecture is used to perform computing tasks, then computing performance is improved, but memory access time limit cannot be overcome
Solution Approach 1:
The patent integrates processing units and data storage areas within the same memory chip, creating a unified structure that eliminates the separation between processing and memory access. This integration allows data to be fetched and processed within the same chip without requiring access to external memory, thereby maintaining high computing performance while overcoming the memory access time limitation.
4Productivity
If a main processor assigns computing tasks to multiple memory chips with processing units, then multiprocessing efficiency is improved, but system complexity is increased
Solution Approach 1:
The patent divides the computing system into multiple memory chips, each containing processing units and data storage areas. This segmentation creates modular units that can independently execute tasks, improving multiprocessing efficiency. The modular structure actually simplifies system management compared to traditional architectures, as each chip is a self-contained unit with integrated processing and storage capabilities.
Solution Approach 2:
The memory chips in the patent are designed to be multi-functional, containing both processing units and data storage areas within the same chip. This universality allows each chip to independently perform both computation and data storage functions, reducing the need for separate specialized components and thereby reducing overall system complexity while maintaining high multiprocessing efficiency.
Data Source
AI summary
A memory processor-based multiprocessing architecture and an operation method thereof are provided. The memory processor-based multiprocessing architecture includes a main processor and a plurality of memory chips. The memory chips include a plurality of processing units and a plurality of data storage areas. The processing units and the data storage areas are respectively disposed one-to-one in the memory chips. The data storage areas are configured to share a plurality of sub-datasets of a large dataset. The main processor assigns a computing task to one of the processing units of the memory chips, so that the one of the processing units accesses the corresponding data storage area to perform the computing task according to a part of the sub-datasets.