Bank-Resident Memory Processor for Low-Latency PIM Control
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Solution Overview
Problem
Existing memory devices face inefficiencies due to external control circuitry, leading to bandwidth bottlenecks and performance degradation, especially in IoT applications where multiple memory devices ingest and transfer data to a host, resulting in increased command transfer times and power consumption.
Innovation Solution
Incorporating a system processor resident on the memory device to control memory operations locally, reducing the need for external command transfers and enabling processing-in-memory (PIM) operations, thereby decreasing command latency and bandwidth requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If memory operations are controlled by external circuitry, then device complexity is reduced, but command transfer time and power consumption increase
Solution Approach 1:
The patent merges the control processor and memory array into a single integrated memory device, allowing the processor to execute instructions directly within the memory device without external command transfers. This combining of functions resolves the contradiction by maintaining low device complexity while eliminating command transfer time delays.
Solution Approach 2:
The patent introduces an intermediary data bus that enables direct communication between memory arrays within the same memory device. This intermediary pathway allows data to be transferred between local memory arrays without requiring external processor intervention, thereby reducing command transfer time while maintaining simplified device architecture.
2Ease of operation
If memory operations are controlled by external circuitry, then ease of operation is improved, but processing performance deteriorates
Solution Approach 1:
The patent segments the memory system into multiple independent memory devices, each with its own integrated control processor. This segmentation allows each device to operate autonomously and process instructions locally, improving processing performance while maintaining ease of operation through standardized interfaces.
Solution Approach 2:
The patent moves the control processor from an external dimension to an internal dimension within the memory device. This dimensional change enables parallel processing across multiple memory devices, each executing instructions independently, thereby enhancing overall processing performance while preserving operational simplicity.
3Productivity
If multiple memory devices transfer data to host, then data throughput is increased, but bandwidth bottlenecks and power consumption increase
Solution Approach 1:
The patent implements preliminary data processing and filtering within each memory device before data transfer to the host. Instructions executed by the integrated processors prepare data in advance, transferring only necessary information to the host. This preliminary action increases effective data throughput while reducing power consumption by minimizing external data transfers.
Solution Approach 2:
Each memory device provides self-service through its integrated control processor, independently managing data preparation and transfer operations. This self-service capability allows memory devices to optimize their own power consumption while contributing to increased overall system throughput, as each device autonomously handles only the data processing required for its specific function.
Data Source
AI summary
An example apparatus includes a memory device comprising a plurality of banks of memory cells. A particular bank of memory cells among the plurality of banks includes a system processor resident on a particular bank of the plurality of banks.