Memory Processor Read Schemes for Lower-Power ANN Data Movement
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Solution Overview
Problem
Existing electronic devices face challenges in efficiently processing artificial neural networks (ANNs) due to high power consumption and inefficient data movement between processors and memory, which hinders performance.
Innovation Solution
A memory device with a memory processor and controller that determines optimal read schemes for data transfer based on operation type, allowing for efficient data relocation and processing using near-memory accelerators to reduce data movement and increase processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred between processors and memory using conventional methods, then processing can be performed, but power consumption increases and processing performance decreases
Solution Approach 1:
The patent combines the processor and memory into a closely integrated architecture where the processor is disposed within or close to the memory. This merging allows the processor to directly access memory without requiring data transfer through external buses, thereby reducing power consumption while maintaining high processing performance for ANN operations.
Solution Approach 2:
The patent introduces a near-memory accelerator as an intermediary component between the processor and memory. This accelerator is specifically designed to handle ANN processing tasks, enabling efficient data movement and computation with reduced power consumption compared to conventional processor-memory architectures.
2Productivity
If data movement between processors and memory is increased to improve processing capability, then processing performance increases, but power consumption increases
Solution Approach 1:
The patent implements preliminary data loading and processing actions within the near-memory environment before data is fully transferred to the main processor. The near-memory accelerator performs preliminary ANN operations on data locally, reducing the amount of data that needs to be moved through high-power external interfaces, thus lowering overall power consumption while maintaining processing capability.
Solution Approach 2:
The patent replaces conventional high-power data transfer mechanisms with more efficient near-memory access methods. By positioning the processor within or close to memory and using a dedicated near-memory accelerator, the system substitutes traditional bus-based data transfer with direct, low-power memory access for ANN processing tasks.
3Productivity
If conventional processor-memory architecture is used, then system simplicity is maintained, but data movement efficiency is poor
Solution Approach 1:
The patent segments the processing system into distinct functional components: a processor for general computation, a near-memory accelerator specifically for ANN operations, and integrated memory structures. This segmentation allows each component to be optimized for its specific function, improving data movement efficiency while managing complexity through modular design.
Solution Approach 2:
The patent adds a new dimensional aspect to the traditional processor-memory hierarchy by introducing the near-memory accelerator layer. This additional dimension enables specialized ANN processing close to memory, improving data movement efficiency without requiring complete redesign of the entire system architecture, thus balancing complexity and performance.
Data Source
AI summary
A memory device and an operating method of the memory device are disclosed. The memory device includes a memory processor including a plurality of processing units (PUs) and a processor controller configured to control the plurality of PUs and a memory controller configured to communicate with the processor controller and control first memory banks. The memory processor is configured to determine, based on a type of an operation performed by the memory processor, a read scheme by which the memory controller reads second data stored in second memory banks of a host device into the first memory banks as first data for the memory processor.