Memory Processor Using Single-Bit Gates for In-Memory Computing
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Solution Overview
Problem
In systems requiring large data computations, such as neural networks, the transmission and processing of data between processors and memory devices often lead to bottlenecks, necessitating the development of in-memory computing (IMC) devices that can perform computations on data stored in memory without the inefficiencies of general-purpose processors.
Innovation Solution
A memory processor method and device that utilize single-bit operation gates to perform operations between vectors, allowing for bit-wise operations and accumulation using a Wallace tree structure, enabling efficient matrix multiplication and similarity calculations through digital implementation, which reduces noise and improves power and area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If general-purpose processors are used to perform neural network computations, then computation capability is achieved, but data transmission bottleneck occurs between processor and memory
Solution Approach 1:
The patent merges memory storage function with computation function by integrating operation gates directly into the memory array. Each memory cell can store not only data but also perform bitwise operations (AND, XOR) on input vectors, eliminating the need for separate processor-memory data transmission for computation operations.
Solution Approach 2:
The patent replaces the traditional von Neumann architecture (processor-memory separation) with an in-memory computing architecture where computation is performed within the memory array itself. This substitutes the mechanical data transmission process with direct computation on stored data, reducing transmission bottleneck.
2Productivity
If in-memory computing devices are used to perform MAC operations, then data transmission bottleneck is reduced, but computational accuracy may be affected by noise
Solution Approach 1:
The patent uses digital logic gates (AND, XOR) that operate on discrete bit values stored in memory cells. These digital operations produce deterministic binary outputs without the continuous noise problems of analog implementations. The Wallace tree structure further processes these digital signals to produce accurate multiplication results.
Solution Approach 2:
The patent replaces analog computation with digital computation by using discrete logic gates and bit-level operations. This substitution eliminates continuous noise interference and provides precise, reproducible computational results while maintaining the in-memory computing advantage of avoiding data transmission bottlenecks.
3Productivity
If analog in-memory computing is used, then computation is performed on stored data, but noise and power consumption increase
Solution Approach 1:
The patent implements digital logic operations (AND, XOR gates) that process binary data stored in memory cells. These digital operations consume significantly less power than analog operations because they operate on discrete bit states rather than continuous voltages, eliminating leakage currents and noise-related energy dissipation.
Solution Approach 2:
The patent substitutes analog signal processing with digital logic operations within the memory array. The use of logic gates and Wallace tree structures for bitwise operations provides energy-efficient computation, as digital logic has well-defined switching characteristics that minimize power consumption compared to continuous analog processing.
4Adaptability or versatility
If multi-bit operations are performed using single-bit operation gates, then computational flexibility is improved, but operation complexity increases
Solution Approach 1:
The patent segments multi-bit operations into sequences of single-bit operations. Each bit of the input vectors is processed independently through AND and XOR gates, with results accumulated through a Wallace tree structure. This segmentation allows complex multi-bit multiplication to be broken down into manageable single-bit operations that can be performed in parallel.
Solution Approach 2:
The patent processes multiple bits simultaneously by applying operations to parallel bit lines within the memory array. The Wallace tree structure efficiently combines partial products from different bit positions, transforming a potentially sequential multi-bit operation into a parallel dimension that reduces overall operation time while maintaining flexibility.
Data Source
AI summary
Provided is a computation method of a memory processor configured to perform an operation between a first vector including first elements and a second vector including second elements, the first elements including respective first bits and the second elements including respective second bits, the method performed by the memory processor including: applying, to single-bit operation gates, the respective first bits and the respective second bits; obtaining bit operation result sum values for the respective first and second elements based on bit operation results obtained using the single-bit operation gates; and obtaining an operation result of the first vector and the second vector based on the bit operation result sum value.