Non-volatile Memory Device with Program Current Clamp
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Solution Overview
Problem
Current non-volatile memory devices face inefficiencies and reliability issues due to the corner effect during channel hot electron injection (CHEI) programming, leading to longer programming times, higher power consumption, and poor reliability, which complicates circuit design and increases array distribution.
Innovation Solution
A non-volatile memory device with a current limiting circuit and a ramped gate voltage is used to program memory cells, limiting the program current and maintaining a high gate injection current throughout the programming process, thereby reducing programming time and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If channel hot electron injection (CHEI) programming is used, then memory cells can be programmed, but programming time increases and reliability deteriorates due to corner effect
Solution Approach 1:
The patent changes the voltage parameter by applying a ramped gate voltage that increases over time during programming. This dynamic voltage adjustment optimizes the injection efficiency of hot electrons into the floating gate, maintaining high programming current throughout the process and reducing programming time while improving reliability by avoiding corner effect issues
Solution Approach 2:
The patent introduces a dynamic programming approach where the gate voltage is ramped during the programming process rather than being fixed. This dynamic adjustment allows the programming current to be maintained at optimal levels throughout, resolving the contradiction between programming speed and reliability
2Reliability
If channel hot electron injection (CHEI) programming is used, then memory cells can be programmed, but power consumption increases
Solution Approach 1:
The patent optimizes power consumption by dynamically adjusting the gate voltage parameter during programming. The ramped voltage profile ensures efficient electron injection throughout the process, reducing the total energy required while maintaining high reliability by avoiding the corner effect
3Productivity
If fixed control line voltage is applied during programming, then circuit design is simplified, but gate injection current decreases leading to slow programming
Solution Approach 1:
The patent employs a dynamic ramped gate voltage control mechanism that automatically adjusts voltage during programming. This dynamic approach maintains high gate injection current throughout the process, achieving fast programming speed while the ramping function can be implemented with relatively simple circuitry
Solution Approach 2:
The patent changes the gate voltage parameter from a fixed value to a time-dependent ramped profile. This parameter transformation maintains high programming current throughout the process, achieving fast programming speeds. The ramping function can be implemented with simple voltage ramping circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables faster and more efficient programming of memory transistors with reduced power consumption and improved reliability by maintaining a high gate injection current and controlling the program current, thus addressing the inefficiencies and reliability issues associated with the corner effect.
Implementation Method 1
a first terminal of the select transistor and a fourth terminal of the memory transistor to limit the program current
Implementation Method 2
CHEI occurs when channel carriers traveling from source to drain of a metal-oxide-semiconductor (MOS) transistor are heated due to drain-source voltage applied across the drain and the source. The hot electrons at the end of the channel have high energy, and are injected into a floating gate of the MOS transistor
Data Source
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AI summary
A method of programming a nonvolatile memory cell (10) which comprises a select transistor (110) and a memory transistor (100) includes applying a preset limit current to a first input of the memory cell (10), applying a limit voltage to a current limiting circuit (1900) electrically connected to a second input of the memory cell (10), applying a limit voltage to stabilize a voltage drop of the memory cell (10), and applying a ramped gate voltage to the memory cell (10) to program the memory cell (10) with a preset limited current determined by the current limiting circuit (1900).