Semiconductor Memory Device Program Loop Voltage Control
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Solution Overview
Problem
Semiconductor memory devices, such as flash memory, face reliability issues due to deteriorated data integrity, particularly in non-volatile memory devices which require improved threshold voltage distribution for enhanced data retention and performance.
Innovation Solution
A semiconductor memory device and method that perform a program loop with a sub-verification voltage lower than the target verification voltage, incrementing the positive voltage supplied to bit lines of memory cells with higher threshold voltages until they exceed the target verification voltage, utilizing page buffers with sub-registers to manage and adjust voltages for improved threshold voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional program operation is performed on memory cells, then data is programmed into the memory cells, but the threshold voltage distribution of the memory cells deteriorates, reducing data reliability
Solution Approach 1:
The program operation is divided into multiple sequential program loops, each targeting specific memory cells based on their threshold voltage characteristics. Memory cells are segmented into different groups (first group with lower threshold voltage, second group with higher threshold voltage) and subjected to different verification voltages and bit line voltage increments, allowing precise control over threshold voltage distribution without compromising data programming reliability
Solution Approach 2:
Different verification voltages (first verification voltage for first group, second verification voltage for second group) and different bit line voltage increment strategies are applied to different memory cell groups based on their local threshold voltage characteristics. This localized approach optimizes the program operation for each group's specific requirements, improving overall threshold voltage distribution while maintaining data reliability
2Reliability
If the positive voltage supplied to the bit line is increased to improve threshold voltage distribution, then data reliability improves, but the complexity of the peripheral circuit increases
Solution Approach 1:
The bit line voltage is made dynamic through incremental adjustment during program loops. The peripheral circuit dynamically increments the bit line voltage by a controlled amount in each program loop based on verification results, allowing adaptive control of threshold voltage distribution without requiring complex static circuit design. This dynamic approach achieves improved reliability while keeping circuit complexity manageable
Solution Approach 2:
A feedback mechanism is implemented where the verification operation results from each program loop feed back to control whether and how much the bit line voltage should be incremented in the next loop. The peripheral circuit uses this feedback to intelligently adjust voltage levels, achieving precise threshold voltage control and improved data reliability without requiring overly complex circuit architecture
Data Source
AI summary
A semiconductor memory device and a method of operating the same perform a program loop, including a program operation and a program verification operation based on a sub-verification voltage smaller than a target verification voltage and the target verification voltage, to the memory cells until a threshold voltage of the memory cells is greater than the target verification voltage. A positive voltage, supplied to the bit line of the memory cell of which the threshold voltage is higher than the sub-verification voltage, is increased whenever the program operation is performed, and thus a threshold voltage distribution of the memory cells may be improved.