Multi-pass Memory Program Operation with Merged Intermediate Levels
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Solution Overview
Problem
Current multi-pass program operations for memory devices, such as the 16-16 scheme for quad-level cells (QLCs), require multiple verify voltages in the coarse program pass, leading to slower program speeds due to increased verify processes and duration, despite offering larger read margins and shorter read times.
Innovation Solution
The solution involves merging multiple intermediate levels in the coarse program pass into one intermediate level, allowing for the use of a single verify voltage for memory cells with different data values, reducing the number and duration of verify processes, and maintaining larger read margins and shorter read times by grouping and verifying memory cells with different data values simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple intermediate levels are used in the coarse program pass, then read margins are improved, but program speed deteriorates due to increased verify processes
Solution Approach 1:
The patent merges multiple intermediate levels (e.g., 4 intermediate levels) into a single intermediate level for the coarse program pass. This consolidation reduces the number of verify voltages required from 4 to 1, thereby decreasing verify process duration and improving program speed while still maintaining adequate read margins through the subsequent fine program pass that establishes the final 16 levels.
2Measurement precision
If multiple verify voltages are used in the coarse program pass, then memory cell verification accuracy is improved, but verify process duration increases
Solution Approach 1:
The patent combines multiple verification operations into a single verify voltage application. Instead of sequentially applying 4 different verify voltages to check 4 intermediate levels, the patent uses one verify voltage to check all memory cells against the single intermediate level, dramatically reducing verify process duration while maintaining verification accuracy through the fine program pass.
Solution Approach 2:
The patent segments the program operation into two distinct passes: a coarse program pass that programs to a single intermediate level with one verify voltage, and a fine program pass that programs to the final 16 levels with multiple verify voltages. This segmentation allows the verify process to be optimized in each pass, reducing overall duration while maintaining accuracy.
3Productivity
If traditional 2N-2N scheme is used, then program speed is maintained, but read margins are reduced
Solution Approach 1:
The patent implements a two-pass program operation that segments the programming process into coarse and fine passes. The coarse pass quickly programs all memory cells to a single intermediate level, maintaining high program speed. The fine pass then programs memory cells to their final destinations among 16 levels, establishing large read margins. This segmentation allows both speed and reliability requirements to be satisfied.
Data Source
AI summary
In certain aspects, a memory device includes a memory cell array having rows of memory cells, word lines respectively coupled to the rows of memory cells, and a peripheral circuit coupled to the memory cell array through the word lines. Each memory cell is configured to store a piece of N-bits data in one of 2N levels, where N is an integer greater than 1. The level corresponds to one of 2N pieces of N-bits data. The peripheral circuit is configured to program, in a first pass, a target memory cell of the memory cells into one of x intermediate levels based on all pages of N pages of the piece of N-bits data to be stored in the target memory cell, where x is an integer smaller than 2N. The peripheral circuit is also configured to program, in a second pass after the first pass, the target memory cell into one of the 2N levels based on all pages of the N pages of the piece of N-bits data to be stored in the target memory cell.