Memory Cell Program Convergence Using Stepped Bias and Pillar Boosting
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Solution Overview
Problem
Existing memory cell programming techniques face challenges in achieving narrow threshold voltage distributions while minimizing time and complexity, particularly in analog program convergence, due to limitations in generating a wide range of data line bias voltages and variations in string current.
Innovation Solution
Implementing multi-step analog program convergence by dividing data line bias voltages into multiple steps for different subsets of memory cells, allowing for a larger range of bias voltages without additional circuitry, and boosting pillars for cells closer to their target threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a wide range of data line bias voltages is generated to achieve narrow threshold voltage distributions, then programming precision is improved, but device complexity increases due to additional circuitry requirements
Solution Approach 1:
The patent segments memory cells into multiple subsets based on their threshold voltage proximity to target levels. Different data line bias voltages are applied to different subsets, allowing precise control of programming for each group without requiring a continuously variable voltage generator, thus reducing circuit complexity while maintaining programming precision.
Solution Approach 2:
The patent applies different bias voltage characteristics to different spatial groups of memory cells based on their local programming needs. Cells closer to their target threshold voltage receive different bias conditions than cells farther from target, enabling precise local control without system-wide complexity.
2Manufacturing precision
If multiple programming steps are used to achieve convergence, then programming precision is improved, but programming time increases
Solution Approach 1:
The patent implements periodic programming pulses with verify operations between them, creating a convergence process that gradually narrows threshold voltage distributions. This multi-step approach achieves high precision while optimizing time by only applying programming pulses when needed for specific cell subsets.
Solution Approach 2:
The patent performs preliminary classification of memory cells into subsets based on their current threshold voltage states before applying programming pulses. This preliminary action enables more efficient subsequent programming steps by targeting only the necessary cell subsets, reducing overall programming time while maintaining precision.
3Reliability
If data line bias voltages are varied to accommodate string current variations, then programming reliability is improved, but control complexity increases
Solution Approach 1:
The patent uses verify operations to detect the current threshold voltage states of memory cells and uses this feedback information to determine subsequent programming actions. This feedback mechanism ensures reliable programming despite string current variations by adapting the programming approach based on actual cell states.
Solution Approach 2:
The patent changes the data line bias voltage parameter in discrete steps corresponding to different cell subsets rather than continuously adjusting it. This approach maintains programming reliability by compensating for string current variations while avoiding the complexity of continuous parameter adjustment circuits.
Data Source
AI summary
Control logic in a memory device initiates a program operation on a memory array of a memory device, the memory array comprising a plurality of memory cells, and the program operation comprising a plurality of program pulses. The control logic further identifies a first subset of the plurality of memory cells and a second subset of the plurality of memory cells based on respective threshold voltages after application of a first program pulse of the plurality of program pulses, and boosts a voltage potential in one or more pillars of the memory array corresponding to the first subset of the plurality of memory cells prior to application of a second program pulse of the plurality of program pulses.