Multi-bit Memory Program Method Using Segmented Verify Voltages
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Solution Overview
Problem
The reliability of multi-bit memory devices is compromised by variations in threshold voltages due to coupling between adjacent memory cells, making it difficult to accurately read data stored through 1-step and coarse program operations, and requiring large buffer memory to retain data until fine program completion.
Innovation Solution
A program method for a multi-bit memory device that involves a coarse-fine programming approach, where verify voltage levels are strategically set to reduce coupling between memory cells, allowing for accurate data reading and reducing the need for large buffer memory by minimizing the amount of data retained during the fine program operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If 1-step and coarse program operations are used to program multi-bit memory devices, then programming speed is improved, but threshold voltage variations due to coupling between adjacent memory cells compromise data reliability
Solution Approach 1:
The program operation is divided into multiple steps (1-step program, coarse program, and fine program operations) with different verify voltage levels. Each step targets specific memory cells with different programming requirements, segmenting the overall programming process to balance speed and reliability.
Solution Approach 2:
Different verify voltage levels are applied at different programming stages. The first verify voltage level is used for initial programming of all memory cells, while the second verify voltage level is used for fine-tuning specific memory cells. This parameter change allows the system to achieve both fast initial programming and reliable final states.
2Reliability
If large buffer memory is used to retain data during fine program operation, then data reliability is improved, but chip area increases
Solution Approach 1:
The patent extracts only the necessary data that needs to be retained during the fine program operation, rather than retaining all programmed data. By identifying and retaining only the minimal required data in the buffer memory, the system maintains reliability while minimizing chip area consumption.
Solution Approach 2:
Data that is not required for the fine program operation is discarded from the buffer memory, while only essential data is retained. This selective retention and discarding approach reduces the buffer memory size needed, thereby reducing overall chip area while maintaining data reliability for the critical fine programming step.
Data Source
AI summary
Provided is a program method of a multi-bit memory device with memory cells arranged in rows and columns. The program method includes a programming each memory cell of the first group of memory cells to a state within a first group of states according to a verify voltage level of a first group of verify voltage levels within a first range of levels, and programming each memory cell of the second group of memory cells to a state within a second group of states according to a verify voltage level of a second group of verify voltage levels within a second range of levels. The lowest verify voltage level in the second range of levels is higher than the highest verify voltage level in the first range of levels. A first voltage difference between adjacent verify voltage levels within the first range of levels is different from a second voltage difference between the highest verify voltage level of the second group of verify voltage levels and the lowest verify voltage level of the third group of verify voltage levels.