Memory Cell Program Voltage Control for Uniform Write Speed
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Solution Overview
Problem
Memory devices experience varying program speeds due to differences in physical column addresses of memory cells, leading to inconsistent performance across the memory cell array.
Innovation Solution
A memory device design that includes control logic to manage program permission voltages based on the magnitude and timing of program voltages, applying these voltages gradually through bit lines to maintain consistent program speed across memory cell groups with varying distances from a reference node.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If program voltages are applied uniformly to all memory cells, then the program operation is simple to control, but memory cells at different physical distances from the reference node experience different program speeds
Solution Approach 1:
The patent applies different program permission voltages to different memory cell groups based on their physical column addresses. Memory cell groups closer to the reference node receive different voltage levels than those farther away, compensating for the inherent speed differences caused by physical distance. This local differentiation ensures uniform program speed across all memory cells while maintaining manageable control through systematic voltage assignment.
2Manufacturing precision
If program permission voltages are adjusted to compensate for physical distance differences, then program speed uniformity is improved, but the control circuit complexity increases
Solution Approach 1:
The patent divides the memory cell array into multiple memory cell groups based on physical column address ranges. Each group is assigned a specific program permission voltage level. This segmentation approach simplifies the control circuit by creating discrete, manageable groups rather than requiring continuous adjustment, reducing overall circuit complexity while achieving uniform program speed across all groups.
Solution Approach 2:
The patent changes the program permission voltage parameter systematically based on the physical column address of memory cell groups. By establishing a clear relationship between physical location and voltage level, the control logic can determine appropriate voltages through address decoding rather than complex real-time measurements, simplifying the control circuit while maintaining program speed uniformity.
3Reliability
If gradual program voltages are applied through word lines, then program operation reliability is improved, but the time required to complete programming increases
Solution Approach 1:
The patent applies program permission voltages to memory cell groups in advance based on their physical column addresses before the actual program voltage is applied. This preliminary voltage assignment ensures that each memory cell group is pre-conditioned with the appropriate voltage level, allowing the gradual program voltage to be applied more efficiently. The pre-positioning of permission voltages maintains reliability while reducing the overall programming time by eliminating delays during the program operation.
Data Source
AI summary
A memory device includes: a memory cell array including a first memory cell group including memory cells located within a first physical distance from a reference node and a second memory cell group including memory cells located beyond the first physical distance from the reference node; a peripheral circuit configured to perform a program operation of applying program voltages increasing gradually to memory cells included in the memory cell array through word lines; and control logic configured to determine a time at which a first program permission voltage is applied to the first memory cell group and determine a magnitude of the first program permission voltage on the basis of a magnitude of the program voltages in response to a gradual increase in the program voltages, the control logic is further configured to control the peripheral circuit to apply the first program permission voltage to the first memory cell group through bit lines.