Nonvolatile Memory Program Verification Stages
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Solution Overview
Problem
The existing incremental step pulse programming (ISPP) scheme for nonvolatile memory devices is hindered by the time-consuming failure bit counting operation, which delays program loops and decreases overall program speed due to the need for extensive verification steps.
Innovation Solution
A program verification method that divides the verification read result into stages, using different reference values for each stage to determine program failure, allowing for early determination of program pass or failure and skipping unnecessary counting operations, thereby reducing overhead and improving program speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional verification method is used that counts all failure bits across all stages, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The patent segments the failure bit counting process into multiple stages, where verification is performed in discrete steps rather than counting all failure bits at once. Each stage counts failure bits for a portion of the memory cells, allowing early termination when a threshold is exceeded, thus reducing total verification time while maintaining accuracy
Solution Approach 2:
The patent performs preliminary verification actions by checking failure bits in early stages before completing the full count. By establishing reference values and comparison thresholds in advance, the system can determine program pass/failure status earlier in the process, avoiding the need to complete exhaustive counting of all failure bits
2Reliability
If extensive verification steps are performed to ensure program accuracy, then reliability is improved, but productivity decreases
Solution Approach 1:
The patent implements dynamic verification by adjusting the verification process based on real-time failure bit counts. The system dynamically determines when to terminate verification by comparing accumulated failure bit counts against reference values, allowing the verification depth to adapt to the actual program status rather than always performing maximum verification steps
Solution Approach 2:
The patent changes verification parameters by using different reference values for different stages of verification. By adjusting these reference values based on program loop iteration and failure patterns, the system optimizes the balance between verification thoroughness and speed, maintaining reliability while improving program throughput
Data Source
AI summary
A program verification method for a nonvolatile memory device includes performing a first failure bit counting operation about a first stage to generate a first failure bit accumulated value and comparing the first failure bit accumulated value and a first failure reference value to determine a program failure. When the first failure bit accumulated value is less than the first failure reference value, a second failure bit counting operation for a second stage is performed to generate a second failure bit accumulated value. The second failure bit accumulated value is compared to a second reference value to determine a program failure. The second failure reference value is different from the first failure reference value.