3D Nonvolatile Memory Program Verification Counter Voltage
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Solution Overview
Problem
The challenge in programming nonvolatile memory devices, such as flash memory, lies in accurately verifying programming states due to capacitive coupling issues, which lead to errors in threshold voltage distributions, especially in multi-level cells, where conventional methods struggle to set precise read voltages with constant margins.
Innovation Solution
A method involving a negative counter voltage applied to a selected word line during the verifying step, with varying voltage levels and durations based on multi-level program states and endurance cycles, is implemented to improve programming accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional program verify method with constant margins is used, then the verification process is simple, but threshold voltage distribution errors occur due to capacitive coupling
Solution Approach 1:
The patent applies preliminary anti-action by introducing a counter voltage to the selected word line before and during the verify operation. This counter voltage compensates for the capacitive coupling effects that would otherwise cause threshold voltage distribution errors, thereby improving measurement precision without significantly complicating the verification process
Solution Approach 2:
The patent changes the voltage parameter of the selected word line by applying a counter voltage that varies based on the program state. This dynamic parameter adjustment allows for accurate verification across different threshold voltage distributions while maintaining a relatively simple verification framework
2Measurement precision
If negative counter voltage is applied during verify operation, then programming verification accuracy is improved, but operation complexity increases
Solution Approach 1:
The patent applies local quality by selectively applying the counter voltage only to the selected word line during the verify operation, rather than uniformly affecting all word lines. This localized approach improves verification accuracy for the specific memory cells being verified while minimizing unnecessary complexity in the overall system operation
Solution Approach 2:
The patent implements feedback by adjusting the counter voltage based on the program state and verification results. The counter voltage is applied for specific durations and at specific timing relative to the verify operation, creating a feedback mechanism that optimizes verification accuracy without requiring complex external control circuitry
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the accuracy of programming verification by adjusting the negative counter voltage according to program loops and endurance cycles, minimizing errors and improving the reliability of multi-level cell programming.
Implementation Method 1
problems due to capacitive coupling between conductive floating gates
Data Source
AI summary
A program method of a three-dimensional nonvolatile memory device is provided which includes executing at least one program loop including an operation of programming selected memory cells of a selected string turned on by a selected string selection transistor and an operation of verifying whether programming of the memory cells is passed; and applying a negative counter voltage to a selected word line connected to the selected memory cells of the selected string at least once during an interval of the verify operation where there are turned on string selection transistors of unselected strings connected through the same bit line as that of the selected string.