Non-volatile Memory Program Verify Skipping
Solution Overview
Problem
Conventional non-volatile memory devices face inefficiencies in program verify operations, particularly in multi-state cells, where the number of programming steps increases with the number of partitions, leading to reduced performance and increased complexity.
Innovation Solution
The implementation of a 'One-bit-Pass' (OBP) operation during program verify, where a first sub-cycle verifies relative to a threshold level below the target, and a second sub-cycle only occurs if any memory cell passes the first threshold, allowing for time-saving by skipping unnecessary verify cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional program verify operations are used with multiple threshold levels for multi-state memory cells, then programming precision is improved, but programming time increases due to the need to perform all verify cycles
Solution Approach 1:
The patent applies the skipping principle by allowing the memory controller to skip the second verify cycle (at the second threshold level) when the first verify cycle (at the first threshold level) already confirms successful programming. This is achieved by monitoring verify results and conditionally eliminating redundant verification steps, thus reducing programming time while maintaining precision through the hierarchical verify structure.
Solution Approach 2:
The patent implements preliminary action by performing verification at a first threshold level before proceeding to verification at a second threshold level. This preliminary verify at the lower threshold provides early feedback on programming status, enabling the system to make informed decisions about whether additional verify cycles are necessary, thereby optimizing the overall programming process.
2Quantity of substance
If the number of partitions in multi-state memory cells increases, then storage capacity is improved, but the number of programming steps increases leading to reduced performance
Solution Approach 1:
The patent applies segmentation by dividing the verification process into multiple hierarchical levels (first threshold level and second threshold level), where each level serves a specific verification purpose. This segmented approach allows the system to efficiently handle multi-state memory cells by breaking down the complex verification task into manageable stages, improving performance despite increased storage capacity requirements.
Solution Approach 2:
The patent implements partial action by performing only the necessary verify cycles based on actual programming needs. When the first verify cycle confirms successful programming, the system performs partial verification (skipping the second cycle) rather than executing all possible verify cycles, thus maintaining productivity while supporting increased storage capacity through multi-state cells.
3Reliability
If additional verify cycles are performed to ensure programming accuracy, then reliability is improved, but device complexity increases due to additional control logic
Solution Approach 1:
The patent applies dynamics by making the verification process adaptive rather than static. The memory controller dynamically adjusts the number of verify cycles performed based on real-time verification results. This dynamic approach allows the system to maintain high reliability through conditional additional verification while avoiding the need for complex predetermined control logic for all possible scenarios.
Solution Approach 2:
The patent implements feedback mechanisms where verify results from the first threshold level are used to control whether the second verify cycle is executed. This feedback-driven approach simplifies control logic by using the outcome of earlier verification steps to determine subsequent actions, thereby maintaining reliability through conditional verification while minimizing device complexity.
Data Source
AI summary
In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of the memory cells, a portion of the verify operation is recognized to be superfluous and skipped. Preferably, in a program verify operation relative to a demarcation threshold level for demarcating between two memory states, the verify operation includes a sequence of two verify sub-cycles, the first sub-cycle performing a verify relative to a first threshold level at a predetermined margin below the demarcation threshold level and the second sub-cycle performing a verify relative to a second threshold level which is identical to the demarcation threshold level. Unlike conventional cases, the second sub-cycle is not performed until any one memory cell of the group has been verified to pass the first threshold.