Memory Program Verify Voltage Offsets for Read Window Budget
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Solution Overview
Problem
Memory devices face challenges in accurately reading cells due to charge coupling and lateral migration effects, which cause shifts in threshold voltages, leading to widened distributions and reduced read window budgets, resulting in increased errors and latency.
Innovation Solution
The solution involves modifying memory access operations by determining the minimum number of programming level groups to adjust parameters, using program verify voltage offsets to compensate for cell-to-cell coupling and lateral migration effects, thereby achieving a sufficient read window budget increase without the need for perfect compensation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If perfect compensation for charge coupling and lateral migration effects is implemented, then read window budget increases and error rates decrease, but resource intensity and time required for memory operations increase significantly
Solution Approach 1:
The patent applies partial compensation by determining the minimum number of programming level groups needed to achieve a sufficient read window budget increase. Instead of implementing perfect compensation across all programming levels, the system identifies and applies offsets only to the necessary subset of groups, thereby achieving acceptable error rates without the full resource cost of complete compensation.
Solution Approach 2:
The patent changes the parameter of program verify voltage by applying voltage offsets to programming level groups. This parameter change allows the system to compensate for charge coupling and lateral migration effects dynamically, adjusting the voltage levels to achieve sufficient read windows while controlling the number of groups compensated to maintain operational efficiency.
2Reliability
If perfect compensation for charge coupling and lateral migration effects is implemented, then read window budget increases and error rates decrease, but computing resources and energy consumption increase
Solution Approach 1:
The system performs partial compensation by selecting the minimum number of programming level groups required to achieve sufficient read window budget. This reduces the computational workload and energy consumption compared to implementing perfect compensation across all programming levels, while still achieving acceptable error rates.
Solution Approach 2:
By changing the program verify voltage parameter through selective offset application to programming level groups, the system achieves the necessary compensation effect with reduced computational effort and lower energy consumption compared to comprehensive compensation approaches.
3Reliability
If program verify voltage offsets are applied to all programming levels, then read window budget increases sufficiently, but device complexity and resource intensity increase
Solution Approach 1:
The patent implements partial compensation by applying voltage offsets only to the minimum number of programming level groups necessary to achieve sufficient read window budget. This reduces the complexity of the compensation mechanism compared to applying offsets to all programming levels, while maintaining adequate reliability.
Solution Approach 2:
The patent segments the programming levels into multiple groups and applies compensation selectively to specific groups rather than uniformly to all levels. This segmentation allows the system to manage complexity by treating different programming level groups independently, applying offsets only where necessary to achieve the desired read window budget.
Data Source
AI summary
Embodiments disclosed can include identifying wordline groups where each wordline group is associated with a corresponding default program verify (PV) voltage for each programming level, and determining, for each wordline group, a maximum read window budget (RWB) increase. They can further include defining a target aggregate RWB increase amount based on the maximum RWB increase, and determining, for each wordline group, a minimum number of memory cell programming level groups with corresponding PV voltage offsets sufficient to reach the target aggregate RWB increase amount. The embodiments can also include grouping the programming levels of a specified memory cell into the minimum number of programming level, and applying, based on the specific programming level group containing a target programming level, a corresponding PV voltage offset during a memory cell access operation.


