Multi-Level Memory Programming With Repeated Analog Verify

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Solution Overview

Problem

Existing memory devices face challenges in achieving precise threshold voltage distributions during programming, leading to read errors and inefficiencies, particularly in multi-level cell programming, due to memory cells not reaching their intended voltages and requiring additional error correction.

Innovation Solution

Implementing level-based programming with multiple analog program verify operations between programming pulses, including an additional analog verify operation to identify and further program memory cells that have failed previous verify operations, using control logic to apply specific voltage levels to bitlines for targeted programming.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If traditional programming operations are used with single verify operations, then programming time is reduced, but threshold voltage distribution precision deteriorates leading to read errors

Engineering Contradiction:
Improvethreshold voltage distribution precisionVSAvoidprogramming time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The programming process is segmented into multiple programming pulses separated by multiple analog program verify operations. Each verify operation targets specific voltage levels (e.g., first analog program verify at 3.6V, second analog program verify at 4.0V), dividing the verification task into discrete stages that collectively ensure precise threshold voltage distribution while managing overall programming time efficiently.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If additional analog verify operations are implemented, then threshold voltage accuracy is improved, but device complexity increases

Engineering Contradiction:
Improveprogram verify accuracyVSAvoidprogramming operation complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

Different analog verify operations target different local voltage ranges with specialized voltage levels. The first analog program verify operation uses a first voltage level (3.6V) optimized for lower threshold voltage verification, while the second analog program verify operation uses a second voltage level (4.0V) optimized for higher threshold voltage verification. This localized optimization ensures high measurement precision for each voltage range without requiring a single complex verify mechanism.

Inventive Principle:
Principle #3Local quality

3Manufacturing precision

If multiple programming pulses are used with level-based programming, then threshold voltage distribution is improved, but programming time increases

Engineering Contradiction:
Improvethreshold voltage distributionVSAvoidprogramming speed
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The programming process employs periodic action through alternating programming pulses and verify operations. The sequence repeats: programming pulse applied to memory cells, then first analog program verify operation, then second analog program verify operation, then another programming pulse. This periodic cycle ensures thorough verification at multiple voltage levels while maintaining efficient programming throughput by systematically rotating through the verification stages.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20260004861A1Level-based programming with multiple analog program verify operations between programming pulses
Publication Date: 2026.01.01 MICRON TECHNOLOGY INC
  • US20260004861A1 patent drawing
  • US20260004861A1 patent drawing
  • US20260004861A1 patent drawing

AI summary

A method includes causing, in between applying programming pulses to selectively store data to multiple voltage levels of a plurality of memory cells, a second occurrence of a first analog verify operation to be performed on a first set of memory cells to identify one or more memory cells of a first subset of the first set of memory cells. The first subset of memory cells are those that failed the first analog verify operation and the one or more memory cells twice failed the first analog verify operation. A first occurrence of a second analog verify operation is performed at a second set of memory cells to identify a second subset of the second set of memory cells that failed the second analog verify operation.