Multi-bit Memory Programming via Group Segmentation and Bias Control
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently programming multi-bit data due to limitations in voltage control and verification processes, leading to reduced operating speed and reliability.
Innovation Solution
A method and semiconductor device configuration that sorts program states of memory cells into groups, applies different bias voltages to bit lines, and uses a program voltage on selected word lines while verifying target states, with inhibition voltages applied to programmed cells to prevent disturbance and optimize programming across multiple groups.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If different bias voltages are applied to bit lines for different groups of memory cells, then programming speed is improved by enabling simultaneous programming of multiple states, but device complexity increases due to the need for voltage control mechanisms
Solution Approach 1:
The patent divides the memory cell array into multiple groups, with each group associated with specific bit lines. Different bias voltages are applied to different groups of bit lines simultaneously, enabling parallel programming of multiple states. This segmentation allows the system to program multiple memory cells in different states concurrently, thereby improving programming speed without requiring complex per-cell control.
Solution Approach 2:
The patent applies different bias voltages to different groups of bit lines based on the specific programming requirements of each group. Each group receives a tailored voltage configuration optimized for its target program state, allowing localized optimization of programming conditions while maintaining overall system efficiency.
2Productivity
If program voltage is applied to selected word lines with different bias voltages on bit lines, then multi-bit data programming efficiency is improved, but energy consumption increases due to multiple voltage levels
Solution Approach 1:
The patent applies program voltage to only the selected word lines that correspond to the current programming operation, rather than activating all word lines. Similarly, bias voltages are applied only to the specific groups of bit lines that are being programmed. This partial action approach improves programming efficiency by focusing energy on the relevant memory cells while minimizing unnecessary energy consumption from inactive lines.
Solution Approach 2:
The patent employs a sequential programming approach where different groups of memory cells are programmed in successive phases. In each phase, specific word lines and bit line groups are activated with appropriate voltages, while others remain inactive. This periodic activation pattern enables efficient multi-bit programming by cycling through different groups, improving overall efficiency while managing energy consumption through controlled, time-separated voltage applications.
3Reliability
If inhibition voltage is applied to bit lines of programmed memory cells, then programming reliability is improved by preventing disturbance to already programmed cells, but programming time increases due to additional voltage application steps
Solution Approach 1:
The patent applies inhibition voltage to bit lines corresponding to already programmed memory cells before or during the programming process of other cells. This preliminary protective action prevents unwanted charge injection or disturbance to previously programmed cells, ensuring programming reliability. By proactively applying inhibition voltage to protected groups, the system maintains data integrity without requiring additional verification steps that would extend programming time.
Solution Approach 2:
The patent prepares the voltage configuration in advance by applying appropriate bias voltages to bit line groups that will be programmed next, while simultaneously maintaining inhibition voltages on groups that are already programmed. This preliminary voltage setup ensures that when programming operations begin, the protective inhibition is already in place, preventing any potential disturbance to programmed cells without adding sequential steps that would increase overall programming time.
4Speed
If multiple groups of memory cells are programmed simultaneously with different bias voltages, then operating speed is enhanced, but measurement precision of program states becomes more difficult to verify
Solution Approach 1:
The patent segments the verification process to match the segmentation of the programming process. Memory cells are verified in groups corresponding to the bit line groups used during programming. By dividing the large memory array into smaller verifiable groups and verifying each group separately with appropriate read voltages, the system maintains measurement precision even while programming multiple groups in parallel. Each group's program state can be accurately verified without interference from other groups.
Solution Approach 2:
The patent applies different read voltages to different groups of bit lines during verification, tailored to the specific program states of each group. This localized verification approach allows each group to be verified with optimal voltage conditions for its target states, maintaining high measurement precision. The control logic selectively activates verification for specific groups based on their programming status, ensuring accurate verification without requiring uniform verification conditions across the entire memory array.
Data Source
AI summary
In a method for operating a semiconductor device, the method may include: sorting program states of a memory cell that stores multi-bit data into a plurality of groups; applying different bias voltages to bit lines corresponding to a selected group among the plurality of groups; applying a program voltage to a selected word line corresponding to the selected group; verifying whether each of selected memory cells corresponding to the selected word line is programmed to a respective target program state; applying an inhibition voltage to bit lines coupled to programmed memory cells; and selecting a next group to be programmed until the plurality of groups are programmed.