Semiconductor Memory Programming Bit Line Precharge Control
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Solution Overview
Problem
In semiconductor memory devices, existing programming methods face challenges in preventing memory cells from being inadvertently programmed when a program voltage is applied, as the gates of memory cells are commonly coupled to word lines, leading to program inhibition issues, particularly with high integration density and the need for efficient data preservation without power supply.
Innovation Solution
The method involves precharging bit lines to varying voltages based on the level of the program voltage, using a series of program voltages applied to selected word lines, and adjusting the pass voltage for unselected word lines to reduce peak current and prevent programming of memory cells intended to remain in an erased state, employing a self-boosting scheme to maintain the desired voltage gaps and prevent programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a program voltage is applied to word lines for programming memory cells, then programming operation is enabled, but memory cells that should remain in erased state are inadvertently programmed
Solution Approach 1:
The patent applies different voltage levels to different bit lines based on their specific function. Selected bit lines receive a first voltage level during programming, while unselected bit lines receive a second voltage level (ground potential). This local differentiation enables the programming operation on selected cells while maintaining erased state on unselected cells, resolving the contradiction between enabling programming and preventing inadvertent programming.
Solution Approach 2:
The patent performs preliminary voltage assignment to bit lines before applying the program voltage to word lines. The selected bit line is precharged to a first voltage level, and unselected bit lines are set to ground potential. This preliminary action ensures that when the program voltage is subsequently applied, only the intended memory cells are programmed, while others remain protected in their erased state.
2Reliability
If high program voltage is applied to achieve reliable programming, then programming effectiveness is improved, but peak current increases
Solution Approach 1:
The patent confines the high program voltage application to only the selected bit line and its associated memory cells, while unselected bit lines are maintained at ground potential. This localized voltage application achieves reliable programming effectiveness for the intended cells while significantly reducing the overall peak current draw compared to applying high voltage across all bit lines simultaneously.
3Ease of operation
If pass voltage is applied to unselected word lines to maintain them in pass state, then word line operation is maintained, but threshold voltage disturbances occur in memory cells
Solution Approach 1:
The patent applies ground potential to unselected bit lines as a preliminary protective measure before word line operations. This preliminary action creates a protective condition that prevents threshold voltage disturbances in memory cells associated with unselected bit lines, while still allowing the pass voltage to be applied to unselected word lines for maintaining their operational state.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the rate of peak current and allows for a lower pass voltage to be applied, effectively preventing unintended programming while maintaining data integrity and reducing disturbances in threshold voltages, thereby enhancing the programming efficiency and data preservation in semiconductor memory devices.
Implementation Method 1
In each memory cell, a threshold voltage is elevated when electrons are charged at the floating gate FG
Implementation Method 2
32 memory cells C0 to C31 are serially connected between a drain selection transistor DST and a source selection transistor SST
Data Source
AI summary
A method of programming a semiconductor memory device by applying a program voltage to a selected word line in an incremental step pulse program mode includes raising a voltage of precharging a bit line for program inhibition according to an increase in the program voltage applied to the selected word line.