3D Nonvolatile Memory Programming with Grouped Bit-Line Timing
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Solution Overview
Problem
Nonvolatile memory devices with three-dimensional structures face increased programming time due to higher integration and memory capacity, leading to performance degradation and program disturbance.
Innovation Solution
A nonvolatile memory device and method that divides program data into multiple groups, discriminates set-up timing of target bit-lines based on group states, and applies program voltages with signal pulses to reduce programming time, using a control circuit to manage voltage levels and pulses for efficient programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integration degree and memory capacity are increased in three-dimensional nonvolatile memory devices, then storage capacity is improved, but programming time increases
Solution Approach 1:
The patent divides program data into multiple groups corresponding to different target states, and divides the cell strings into multiple groups. Each group is programmed concurrently with optimized voltage application timing. This segmentation allows parallel processing of multiple data groups, reducing overall programming time while maintaining high capacity.
Solution Approach 2:
The patent applies program pass voltage to unselected word lines before applying program voltage to the selected word line. This preliminary action prepares the unselected cell strings by raising their channel voltage, preventing program disturbance while allowing the selected cell strings to be programmed efficiently. The timing discrimination of bit-line set-up further optimizes this preliminary preparation.
2Quantity of substance
If integration degree is increased in three-dimensional nonvolatile memory devices, then memory density is improved, but program disturbance occurs
Solution Approach 1:
The patent applies program pass voltage to unselected word lines before applying program voltage to the selected word line. This preliminary action prepares the unselected cell strings by raising their channel voltage, preventing program disturbance while allowing the selected cell strings to be programmed efficiently.
Solution Approach 2:
The patent dynamically adjusts the timing of bit-line set-up for different target states by discriminating set-up timing based on target states during the program execution period. This dynamic timing adjustment optimizes voltage application for each group, preventing program disturbance in unselected cell strings while maintaining programming efficiency.
3Productivity
If multiple states are programmed concurrently, then programming speed is improved, but voltage control complexity increases
Solution Approach 1:
The patent segments program data into multiple groups corresponding to different target states, with each group having optimized set-up timing. This segmentation allows concurrent programming of multiple states while managing voltage control complexity through systematic timing discrimination for each group.
Data Source
AI summary
A nonvolatile memory device includes a memory block and a control circuit. The memory block includes cell strings. The control circuit controls a first program operation by dividing program data having threshold voltage distributions which have a plurality of states into a plurality of groups, discharging target bit-lines coupled to selected cell strings corresponding to the groups to a ground voltage during a bit-line set-up period of a program loop, discriminating a set-up timing of each of the target bit-lines based on target states of the groups during a first sub period, in which a program voltage and a program pass voltage are ramping and applying the program voltage with a signal pulse having a second target level to a selected word-line, while applying the program pass voltage having a first target level to unselected word-lines, during a second sub period.