Non-Volatile Memory Programming Circuit for Analog In-Situ Computing
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Solution Overview
Problem
Existing non-volatile memory devices, particularly RRAM, require inefficient analog-to-digital and digital-to-analog conversions and intermediate memory read/write operations for in-situ computing algorithms, leading to high energy consumption and complexity in implementing Markov chain Monte Carlo sampling and other in-memory computing applications.
Innovation Solution
A memory programming circuit that uses a single analog circuit with multiplexing and de-multiplexing capabilities to perform programming operations in parallel across alternating rows of a non-volatile memory array, eliminating the need for conversions by connecting source lines to odd and even rows differently and applying signal transformation functions to output signals for programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If analog-to-digital and digital-to-analog conversions are performed for in-situ computing algorithms, then computing functionality is enabled, but energy consumption increases and system complexity increases
Solution Approach 1:
The patent extracts and eliminates the analog-to-digital and digital-to-analog conversion stages from the in-situ computing pipeline. By directly using analog signals from the memory array for computing operations and writing results back in analog form, the system enables computing functionality while removing the energy-consuming conversion processes that traditionally bridged analog memory and digital processing.
Solution Approach 2:
The patent introduces a specialized read circuit that acts as an intermediary between the memory array and computing units. This read circuit directly outputs analog signals that can be used for computing operations without requiring full analog-to-digital conversion, thereby enabling computing functionality while reducing energy consumption compared to traditional conversion-based approaches.
2Adaptability or versatility
If analog-to-digital and digital-to-analog conversions are performed for in-situ computing algorithms, then computing functionality is enabled, but device complexity increases
Solution Approach 1:
The patent removes the complex analog-to-digital and digital-to-analog conversion infrastructure from the system architecture. By enabling direct analog computing operations on memory array outputs, the system achieves computing functionality while significantly reducing device complexity by eliminating entire conversion subsystems and their associated control logic.
Solution Approach 2:
The patent makes the memory array serve multiple functions: it acts as both storage and computing input simultaneously. The same memory structure that stores data also directly provides analog signals for computing operations, eliminating the need for separate conversion circuits and reducing overall system complexity while maintaining computing functionality.
3Adaptability or versatility
If intermediate memory read/write operations are performed for in-situ computing algorithms, then computing operations can be executed, but energy consumption increases
Solution Approach 1:
The patent establishes a continuous analog signal flow from the memory array directly to the computing units and back to memory for result storage. This continuous action eliminates the need for intermediate read/write operations that would convert analog signals to digital and back, thereby enabling computing operations while maintaining energy efficiency through uninterrupted analog signal processing.
4Productivity
If multiple source lines are used to connect to alternating rows of memory units, then programming efficiency is improved, but device complexity increases
Solution Approach 1:
The patent segments the memory array into alternating row groups (odd rows and even rows) that can be independently addressed by different source lines. This segmentation enables parallel programming operations where multiple rows can be programmed simultaneously, improving programming efficiency while the modular nature of the segmentation keeps the added circuit complexity manageable and organized.
Solution Approach 2:
The patent adds a row-group dimension to the addressing scheme by introducing multiple source lines that target specific row parities (odd/even). This dimensional extension to the address space enables parallel access to different row groups, significantly improving programming efficiency while the regular pattern of alternating row assignment keeps the control logic relatively simple.
Data Source
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AI summary
A memory programming circuit for programming a non-volatile memory device (30) having an array structure comprising a plurality of rows, each row having a row index and comprising one or more memory units (35), each memory unit (35) being configured to receive one or more input signals and to deliver one or more output signals, the memory programming circuit comprising: - a first source line (31) connected to the top electrode of the memory units (35) comprised at rows of odd row indices, and - a second source line (32) connected to the top electrodes of the memory units (35) comprised at rows of even row indices.