Non-Volatile Memory Programming Method for Capacitive Coupling Interference
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Solution Overview
Problem
Non-volatile memory devices, particularly Flash memory devices, face issues with memory cell to memory cell coupling during programming, which can interfere with stored data values due to capacitive coupling effects, especially in modern NAND architecture with smaller cell separation and low operating voltages, leading to program disturb and data corruption.
Innovation Solution
The solution involves adjusting the threshold voltage level of one memory cell based on the coupling ratio and data being programmed in an adjacent cell, allowing the coupling effect to bring the first memory cell to its target programming level, thereby compensating for capacitive coupling interference and maintaining accurate data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell separation is reduced to increase storage density, then storage capacity is improved, but capacitive coupling interference between adjacent cells increases
Solution Approach 1:
The patent applies preliminary anti-action by adjusting the programming voltage of first memory cells before programming adjacent second memory cells. The control logic detects when a second cell is to be programmed and preemptively adjusts the voltage for adjacent first cells to compensate for the capacitive coupling that will occur during the second cell's programming operation.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the programming voltage parameter based on the programming status of adjacent memory cells. The control logic modifies the voltage level applied to first memory cells depending on whether neighboring second memory cells are being programmed, thereby adapting the electrical parameters to minimize coupling interference.
2Productivity
If programming voltage is increased to improve programming speed, then programming efficiency is improved, but capacitive coupling disturbance to adjacent cells increases
Solution Approach 1:
The patent applies dynamics by making the programming voltage adaptive rather than static. The control logic continuously monitors the programming status of adjacent memory cells and dynamically adjusts the programming voltage for each cell based on real-time conditions, optimizing both speed and interference reduction.
Solution Approach 2:
The patent implements local quality by applying different programming voltages to different memory cells based on their specific spatial relationships and programming status. Instead of using a uniform voltage for all cells, the control logic tailors the voltage level to each cell's local context, reducing disturbance to adjacent cells while maintaining programming efficiency.
3Productivity
If multiple memory cells are programmed simultaneously to improve throughput, then programming throughput is improved, but mutual interference between cells increases
Solution Approach 1:
The patent applies feedback by implementing a control logic that monitors the programming status of memory cells and uses this information to adjust programming parameters. The system detects when adjacent cells are being programmed and feeds this information back to modify the voltage applied to neighboring cells, thereby managing interference while maintaining throughput.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the impact of capacitive coupling on stored data values, ensuring that threshold voltages remain within the desired logic window, thereby preventing data corruption and maintaining reliable programming in non-volatile memory devices.
Implementation Method 1
memory cell to memory cell coupling during the programming of adjacent cells of the row or the programming of memory cells of adjacent word lines or rows, interfering with or even program disturbing the coupled memory cell
Data Source
AI summary
A non-volatile memory device and programming process is described that compensates for coupling effects on threshold gate voltages of adjacent floating gate or non-conductive floating node memory cells by adjusting the threshold voltage level programmed in view of the data being programmed on a following programming cycle into adjacent memory cells, so that the coupling effect results in the desired target threshold voltages for the cells. In one embodiment of the present invention, memory cell coupling is compensated for by adjusting programming level of one or more memory cells of a first page a memory array to a higher or lower threshold verify target voltage given the data/programming level to be written to directly adjacent memory cells of a second page, so that coupling between the directly adjacent memory cells of the first and second pages brings the memory cells of first page to their final target programming level.