Multi-Stage Non-Volatile Memory Programming With Charge De-Trapping Delay

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Solution Overview

Problem

The increased density and tightened tolerances between partitioned voltage ranges in multi-state memory structures lead to prominent parasitic electrical behaviors that negatively impact programming and data reliability in non-volatile memory systems.

Innovation Solution

Implementing a multi-stage programming approach with a time delay between programming stages, using a programming algorithm that includes a first and second programming stage, and applying a predetermined time delay to manage parasitic effects and improve data reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multi-state memory structures are used to increase storage density, then storage capacity is improved, but parasitic electrical behaviors worsen and negatively impact programming and data reliability

Engineering Contradiction:

Improvestorage densityVSAvoiddata reliability

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The programming process is divided into multiple distinct stages (first programming stage, second programming stage) with different voltage levels and durations. This segmentation allows each stage to address specific aspects of charge trapping separately, improving overall programming reliability in multi-state memory structures while maintaining high storage density

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A time delay is introduced between the first and second programming stages to allow unintentionally trapped charges to de-trap before the second programming stage begins. This preliminary action prevents parasitic effects from compromising the final programmed state, thereby improving data reliability without reducing storage capacity

Inventive Principle:

Principle #10Preliminary action

2Reliability

If multi-stage programming is implemented to improve data reliability, then programming time increases

Engineering Contradiction:

Improveprogramming reliabilityVSAvoidprogramming time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The programming process uses periodic action by introducing a time delay between programming stages. This delay allows parasitic effects to subside naturally without requiring extended programming durations, thus maintaining programming reliability while minimizing time loss through optimized periodic cycling of voltage applications

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS12499946B2Reliability improvement through delay between multi-stage programming steps in non-volatile memory structures

Publication Date: 2025.12.16 SANDISK TECHNOLOGIES LLC

AI summary

A method for multi-stage programming of a non-volatile memory structure includes the step of initiating a programming operation with respect to a memory block. The method also includes the step of applying a programming algorithm to the memory block. The programming algorithm comprises at least a first programming stage and a second programming stage. Between the first programming stage and the second programming stage, the method additionally includes applying a time delay according to a pre-determined amount of time. Further, the pre-determined amount of time may be defined as the amount of time that, according to a probabilistic function, permits de-trapping of any charges unintentionally trapped within a memory cell of the memory block as a result of the first programming stage.