Nonvolatile Memory Programming Error Control

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Solution Overview

Problem

NAND type flash memory devices face programming errors due to threshold voltage shifts in adjacent memory cells caused by capacitive coupling and GIDL effects, leading to inaccurate data storage and increased error rates.

Innovation Solution

A nonvolatile semiconductor memory device with a memory cell array, voltage generator circuit, counter circuit, storage circuit, comparison circuit, and control circuit that uses multiple verify voltage pulses and step-up programming methods to accurately control threshold levels, reducing programming errors by adjusting verify voltages based on the number of programming pulses applied.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a high voltage programming voltage is applied to program a memory cell in a higher voltage region, then the memory cell can be programmed to higher threshold levels, but the threshold of an adjacent memory cell shifts to a higher voltage region causing programming errors

Engineering Contradiction:

Improveprogramming precisionVSAvoidprogramming reliability

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The patent segments the programming process into multiple stages with different verify voltages. Instead of using a single high verify voltage throughout, the system uses a first verify voltage for initial programming and a second verify voltage (lower than the first) for subsequent verification. This segmentation prevents threshold shifts in adjacent cells from causing false failures while maintaining programming precision.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent dynamically adjusts the verify voltage based on the programming state. The control circuit switches between different verify voltages depending on whether the memory cell has been programmed using the first or second programming method. This dynamic adjustment allows the system to adapt to different programming stages and prevent false programming errors.

Inventive Principle:

Principle #15Dynamics

2Manufacturing precision

If multiple verify voltage pulses are used to control threshold levels, then programming accuracy is improved, but the programming time and process complexity increase

Engineering Contradiction:

Improvethreshold control precisionVSAvoidprogramming time

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent applies partial action by using a two-stage verify voltage approach rather than exhaustive multiple verification steps. The first verify voltage provides initial verification, and the second verify voltage provides additional verification only when needed. This partial verification approach reduces programming time compared to using multiple high verify voltage pulses throughout the entire process.

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The patent changes the verify voltage parameter dynamically during the programming process. The control circuit adjusts the verify voltage from a first level to a second level based on the programming method being used. This parameter change allows the system to maintain precision while reducing the overall time required for verification.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces programming errors by precisely controlling threshold voltages, ensuring accurate data storage and improving the controllability of memory cell thresholds, even in the presence of capacitive coupling and GIDL effects.

Implementation Method 1

capacitive coupling between the floating gate of a memory cell and the floating gate of an adjacent memory cell

Methodology Applied

Scientific EffectCapacitive coupling: Capacitance

Implementation Method 2

GIDL effects

Methodology Applied

Scientific EffectGIDL effect:

Data Source

PatentUS7590007B2Nonvolatile semiconductor memory device

Publication Date: 2009.09.15 KIOXIA CORP

AI summary

A nonvolatile semiconductor memory device includes a memory cell array including a plurality of memory cells each having a plurality of threshold levels corresponding to a plurality of programming data respectively; a voltage generator circuit which generates a plurality of programming voltage pulses and a plurality of verify voltage pulses which are applied to said nonvolatile memory cells; a counter circuit which counts the number of times said programming voltage pulse is applied to corresponding said nonvolatile memory cell; a storage circuit which stores data corresponding to said plurality of verify voltage pulses which are set for each of corresponding said threshold levels and the number of times said programming voltage pulse is applied, the number of times said programming voltage pulse is applied being standards for switching a plurality of said verify voltage pulses; a comparison circuit which compares the number of times said programming voltage pulse is applied with said standards and generates a comparison result; a control circuit which controls said plurality of verify voltage pulses step by step based on said comparison result.