Semiconductor Memory Device Programming Efficiency
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently programming memory cells due to variations in program speed among cells, leading to increased verification times and potential over-programming.
Innovation Solution
The method involves dummy-programming memory cells and dividing them into groups based on threshold voltages, applying different bit line voltages to each group to adjust program speed, and performing verify operations using a reduced number of verify voltages to minimize verification time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all selected memory cells are programmed using the same bit line voltage, then the programming process is simple, but cells with different threshold voltages experience varying program speeds leading to over-programming and increased verification time
Solution Approach 1:
The patent segments selected memory cells into multiple groups based on their threshold voltages measured during dummy-programming. Cells are divided into a first group with threshold voltages ≤ reference threshold voltage and a second group with threshold voltages > reference threshold voltage. Different bit line voltages are applied to each group during programming to control program speed and prevent over-programming, thereby improving threshold voltage distribution control while maintaining programming efficiency.
Solution Approach 2:
The patent applies different bit line voltages to different groups of memory cells based on their local threshold voltage characteristics. The first group receives a first bit line voltage while the second group receives a second bit line voltage, allowing each group to be programmed at an optimal speed suited to its threshold voltage range, thus preventing over-programming and reducing verification time.
2Manufacturing precision
If multiple verify voltages are applied to ensure accurate programming, then programming precision is improved, but verification time increases
Solution Approach 1:
The patent performs dummy-programming of all selected memory cells before the actual programming operation. During this preliminary phase, threshold voltages are measured and used to classify cells into different groups. This preliminary classification enables the subsequent programming operation to use optimized bit line voltages for each group, reducing the need for extensive verification and thereby reducing verification time while maintaining programming accuracy.
Solution Approach 2:
The patent uses feedback from the dummy-programming phase where threshold voltages are measured and fed back to determine the grouping and bit line voltage selection for actual programming. This feedback mechanism ensures that cells are programmed with appropriate voltages from the start, reducing the need for multiple verification passes and thus reducing verification time while maintaining accuracy.
3Measurement precision
If dummy-programming is performed on all selected memory cells, then threshold voltage measurement accuracy is improved, but additional programming time is required
Solution Approach 1:
The patent performs dummy-programming on all selected memory cells to ensure accurate threshold voltage measurement for grouping purposes. While this appears to be excessive action, it enables precise classification into groups that will be programmed with optimized voltages, ultimately reducing total time by minimizing verification iterations and preventing re-programming due to over-programming.
Data Source
AI summary
A method of operating a semiconductor memory device includes dummy-programming selected memory cells representing all the memory cells to be programmed for a programming operation. The method also includes determining as a first group of memory cells those selected memory cells having threshold voltages less than or equal to a reference threshold voltage and determining as a second group of memory cells those selected memory cells having threshold voltages greater than the reference threshold voltage. The method further includes programming the selected memory cells by applying a first bit line voltage to the memory cells of the first group, applying a second bit line voltage different from the first bit line voltage to the memory cells of the second group, and applying a same program pulse to the memory cells of the first and second groups.