Memory Programming Mitigates Kink Effect via Adjacent Bit Line Inhibit Status
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Solution Overview
Problem
In Adjacent Bit Line (ABL) programming architectures for multi-level cell (MLC) memories, a 'kink effect' occurs where the change in threshold voltage of a cell is disproportionately large, leading to overprogramming and potential cell failure due to large capacitive coupling when adjacent bit lines are inhibited.
Innovation Solution
Implementing a method that uses knowledge of the inhibit status of adjacent bit lines to apply intermediate voltages to the target bit line, slowing down programming when either one or both adjacent bit lines are inhibited, thereby reducing the kink effect. This involves a communication stage between page buffers to determine and communicate the inhibit status, and adjusting programming voltages accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If ABL programming is used to program all bit lines simultaneously, then programming speed is improved, but the kink effect occurs causing overprogramming and cell failure
Solution Approach 1:
The patent applies different programming strategies to different bit lines based on their local conditions. Specifically, it identifies bit lines adjacent to inhibited bit lines (which are prone to kink effect) and applies a different programming pulse sequence to these bit lines compared to normal bit lines. This local differentiation allows the system to maintain high-speed ABL programming for most bit lines while applying protective measures only where needed, thus resolving the contradiction between speed and reliability.
Solution Approach 2:
The patent performs preliminary identification of bit lines that are adjacent to inhibited bit lines before the programming operation begins. By knowing in advance which bit lines are at risk of kink effect, the system can prepare appropriate programming pulses and apply them preventively during the programming process. This preliminary action allows the system to avoid overprogramming before it occurs, maintaining both speed and reliability.
2Loss of time
If programming pulse is applied when adjacent bit lines are inhibited, then programming is completed faster, but large ΔVt movement causes overprogramming
Solution Approach 1:
The patent modifies the programming pulse characteristics specifically for bit lines adjacent to inhibited bit lines, while maintaining standard programming pulses for other bit lines. This localized modification ensures that threshold voltage changes remain within acceptable ranges for vulnerable bit lines without slowing down the overall programming process. The system thus achieves both fast programming and precise threshold voltage control by applying different pulse qualities to different bit lines.
Solution Approach 2:
The patent uses information about the inhibit status of adjacent bit lines to adjust the programming pulse applied to target bit lines. This feedback mechanism allows the system to detect when a bit line is adjacent to an inhibited bit line and automatically adjust the programming parameters accordingly, preventing excessive threshold voltage movement while maintaining programming speed. The feedback loop ensures both time efficiency and voltage control precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces the kink effect by compensating for the inhibit status of adjacent bit lines, preventing overprogramming and ensuring stable threshold voltage changes, thus maintaining memory cell integrity.
Implementation Method 1
large capacitive coupling when adjacent bit lines are inhibited
Data Source
AI summary
Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.