Memory Programming Loops with Adaptive Column Voltage Verification
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Solution Overview
Problem
Existing memory devices face challenges in efficiently programming memory cells, particularly in ensuring accurate and complete programming of multiple states without excessive power consumption or operational inefficiencies.
Innovation Solution
A memory device and method that includes a program loop with a program operation and verification operation, applying multiple verification voltages to check various program states, and adjusting column voltages based on verification results to ensure complete programming, using a control circuit and logic to manage these operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple verification voltages are applied to check multiple program states, then programming accuracy is improved, but operational complexity increases
Solution Approach 1:
The verification process is segmented into multiple stages, where each verification voltage checks a specific program state threshold. This divides the complex verification task into manageable steps, allowing accurate detection of multiple program states without overwhelming complexity in a single operation.
Solution Approach 2:
The control circuit applies verification voltages in a predetermined sequence before final programming confirmation. This preliminary verification ensures that each program state is properly established and detected before proceeding to the next state, improving accuracy while managing operational complexity through structured sequencing.
2Reliability
If program loops are repeated until programming is completed, then programming reliability is improved, but time consumption increases
Solution Approach 1:
The control circuit uses verification results as feedback to determine whether to continue the program loop. After each verification, the circuit checks whether the programming is complete or if additional loops are needed. This feedback mechanism ensures reliable programming completion while minimizing unnecessary time consumption by stopping the loop once programming is confirmed.
Solution Approach 2:
The program loop structure is made dynamic, allowing the number of iterations to vary based on actual programming requirements. The loop continues only as long as verification fails, adapting the time consumption to the actual need for reliability rather than using a fixed maximum number of attempts.
3Manufacturing precision
If column voltages are adjusted based on verification results, then programming precision is improved, but control complexity increases
Solution Approach 1:
The column voltage adjustment is made dynamic based on verification results. The control circuit modifies voltage levels in subsequent program loops according to what was verified in previous loops, allowing precise programming adaptation without requiring complex predetermined voltage sequences for all possible states.
Solution Approach 2:
The control circuit changes voltage parameters (column voltages) based on verification outcomes. By adjusting voltage levels as a function of verification results rather than using fixed predetermined values, the system achieves programming precision while managing control complexity through conditional parameter modification.
Data Source
AI summary
A memory device may include: a control circuit suitable for performing a program loop including a program operation including a program voltage application operation on a selected word line and a bit line setup operation on a plurality of bit lines and a verification operation of applying (N−1) first verification voltages to the selected word line according to a predetermined order to check N types of first program states for each of a plurality of memory cells included in the selected word line; and control logic suitable for controlling the control circuit to repeatedly perform the program loop until programming for the selected word line is completed, and controlling the control circuit to apply any one of N types of column voltages to each of the plurality of bit lines in the bit line setup operation included in a second program loop.