Semiconductor Memory Device Multi-Level Cell Programming
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Solution Overview
Problem
As semiconductor memory devices advance from single level cell (SLC) to multi level cell (MLC), triple level cell (TLC), and quadruple level cell (QLC) modes, they require more complex operations, leading to increased program operating time and reduced device lifespan due to wider threshold voltage distribution widths.
Innovation Solution
A method for operating semiconductor memory devices that involves performing first, second, and third program operations to increase threshold voltages of memory cells to target levels, using different verify voltages to verify and divide threshold voltage distributions, and applying incremental step pulse programming to reduce program time and voltage distribution width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi level cell (MLC), triple level cell (TLC), or quadruple level cell (QLC) mode is used to store more than one bit of information in a single memory cell, then data capacity is increased, but program operating time is increased and device lifespan is reduced
Solution Approach 1:
The patent segments the program operation into multiple distinct phases: a first program operation that simultaneously increases threshold voltages to sub-levels, a second program operation that divides threshold voltages into separate distributions, and a third program operation that increases threshold voltages to final target levels. This segmentation allows complex multi-bit programming to be broken down into manageable steps, reducing overall program time while maintaining high data capacity.
Solution Approach 2:
The first program operation performs preliminary action by increasing threshold voltages of memory cells with different target levels to common or different sub-levels lower than their respective target levels. This preliminary programming step prepares the memory cells for subsequent verification and final programming, enabling more efficient multi-bit storage without proportionally increasing total program time.
2Quantity of substance
If multi level cell (MLC), triple level cell (TLC), or quadruple level cell (QLC) mode is used to store more than one bit of information in a single memory cell, then data capacity is increased, but threshold voltage distribution width is increased
Solution Approach 1:
The patent segments the threshold voltage programming into distinct phases with intermediate verification steps. The second program operation specifically divides threshold voltages into separate distributions for different data states, ensuring that each multi-bit state has a well-defined and narrow threshold voltage distribution. This segmented approach prevents the threshold voltage distributions from overlapping excessively, maintaining manufacturing precision even as data capacity increases.
Solution Approach 2:
The patent incorporates verification operations between programming steps. After the first program operation increases threshold voltages to sub-levels, a verification operation checks the threshold voltage distribution. This feedback mechanism allows the system to adjust subsequent programming parameters to achieve the desired narrow distribution width, ensuring high precision in multi-level cell programming.
Data Source
AI summary
A method of operating a semiconductor memory device includes performing a first program operation to simultaneously increase threshold voltages of memory cells having different target levels to sub-levels lower than the different target levels, verifying the memory cells by using different verify voltages, respectively, performing a second program operation to divide the threshold voltages of the memory cells, and performing a third program operation to increase the threshold voltages of the memory cells to the different target levels, respectively.