Multi-Plane Non-Volatile Memory Programming for Neighbor Plane Disturb
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Solution Overview
Problem
Non-volatile memory systems face issues with neighbor plane disturb during concurrent programming, leading to errors and unreliable data retrieval.
Innovation Solution
Implement a system that monitors and adjusts programming based on threshold voltage distributions, using early program termination mode to prevent disturbances between planes by identifying slower programming in one plane and adjusting operations accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If concurrent programming is performed in multiple planes, then productivity is improved, but neighbor plane disturb causes errors and reduces reliability
Solution Approach 1:
The patent applies preliminary action by performing a test programming operation before the actual concurrent programming. During this test phase, the system identifies which plane programs slower by monitoring threshold voltage distributions. This advance identification allows the system to prepare compensatory measures (adjusted verify conditions) before the actual data programming begins, preventing neighbor plane disturb errors from occurring in the first place.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the verify conditions for different planes based on their programming characteristics. Specifically, the system modifies the threshold voltage verify levels and timing parameters for each plane individually. For the plane identified as programming slower, the system applies more lenient verify conditions, while the faster plane uses stricter conditions. This parameter adaptation allows both planes to be programmed concurrently without causing neighbor plane disturb errors.
2Manufacturing precision
If verify conditions are made stricter to detect programming completion, then manufacturing precision is improved, but programming time increases
Solution Approach 1:
The patent applies local quality by implementing different verify conditions for different planes based on their individual characteristics. Instead of using uniform strict verify conditions for all planes, the system tailors the verify stringency to each plane's programming speed. The faster plane receives stricter verify conditions to ensure precision, while the slower plane receives adjusted conditions that match its programming rate. This localized verification approach maintains high precision where needed without unnecessarily extending the overall programming time.
Solution Approach 2:
The patent implements dynamics by making the verify conditions adaptive rather than static. The system dynamically determines the appropriate verify parameters based on real-time monitoring of threshold voltage distributions during test programming. This dynamic adjustment allows the verify conditions to optimize between precision and speed for each plane, preventing the need to use overly strict conditions for all planes which would unnecessarily extend programming time.
Data Source
AI summary
A non-volatile storage apparatus comprises memory cells organized into multiple planes. To prevent one plane from disturbing another plane while concurrently programming memory cells in a first plane and memory cells in a second plane, the system determines that the memory cells in the second plane are programming slower than the memory cells of the first plane, tests whether the memory cells in the first plane have threshold voltages greater than a test level that is higher than a target verify level, determines that the memory cells in the first plane failed programming if more than a maximum number of the memory cells in the first plane have threshold voltages greater than the test level, and determines that the memory cells in the second plane failed programming if not more than a maximum number of the memory cells of the fast plane have threshold voltages greater than the test level.