Memory Programming Power Loss Immunity via Bitline Biasing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory programming methods are susceptible to data loss during power loss events, particularly during the second pass of the two-pass programming algorithm in non-volatile memory devices, which can result in the loss of lower page (LP) data.
Innovation Solution
Applying varying bias voltage levels to bitlines based on the state of page buffer latches, resulting in slightly lower threshold voltage levels for certain bits, thereby increasing the distribution valleys and ensuring the immunity of lower page (LP) and upper page (UP) data during asynchronous power loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two-pass programming algorithm is used to increase programming speed, then productivity is improved, but reliability deteriorates due to susceptibility to power loss events
Solution Approach 1:
The patent applies preliminary action by performing a first programming pass that programs the lower page data before the second pass programs the upper page data. This preliminary programming ensures that critical lower page data is stored in a stable state before subsequent operations, preventing data loss during power loss events while maintaining the speed benefits of two-pass programming.
Solution Approach 2:
The patent segments the programming operation into two distinct passes: a first pass that programs lower page data with specific voltage conditions, and a second pass that programs upper page data. This segmentation allows each pass to be optimized independently, ensuring data integrity in the first pass while maintaining overall programming efficiency.
2Manufacturing precision
If bias voltage is applied to all bitlines during programming, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by selectively applying different bias voltage conditions to different groups of bitlines based on which pages are being programmed. During the first programming pass, only bitlines associated with lower page data receive specific bias voltages, while bitlines for upper page data remain at standard voltage levels. This localized voltage control achieves precise threshold voltage distribution without requiring complex system-wide voltage control.
Solution Approach 2:
The patent applies partial action by applying enhanced bias voltage conditions only to the extent necessary for the current programming pass. During the first pass, bias voltages are applied only to bitlines involved in lower page programming, and during the second pass, only to bitlines involved in upper page programming, avoiding unnecessary voltage control complexity.
Data Source
AI summary
Described are systems and methods for providing power loss immunity in memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: causing a programming pulse to be applied to to one or more wordlines of the memory array; responsive to determining that a threshold voltage of one or more memory cells of the memory array has reached a pre-program verify level, causing a first bias voltage level to be applied to a first subset of bitlines of the memory array and causing a second bias voltage level to be applied to a second subset of bitlines of the memory array.